Refresh system for a page addressable memory

Details Refresh system for a page addressable memory Refresh system for a page addressable memory

1985-04-01

1987-10-20

Zache, Raulfe B.

Boots, shoes, and leggings

365222, G06F 1216

Patent

active

047018437

ABSTRACT:
A computer memory including a memory subsystem controller having a circuit for providing a plurality of block select signals and a raw address. A plurality of memory blocks is provided, with one of the memory blocks being provided for each of the block select signals from the memory subsystem controller. Each of the memory blocks includes random access memory (RAM) devices for storing data, and a refresh circuit for refreshing its associated RAM devices independent of the refreshing of the RAM devices of the other blocks. The refreshing of the refresh circuit occurs, if possible, when its associated memory block is not selected by its corresponding block select signal from the memory subsystem controller. A re-establishing circuit is included in each memory block which receives a row address from the memory subsystem controller and re-establishes the received row address in its RAM devices after they have been refreshed.

REFERENCES:
patent: 3846765 (1974-11-01), De Vries
patent: 4106108 (1978-08-01), Cislaghi et al.
patent: 4172282 (1979-10-01), Aichelmann et al.
patent: 4238842 (1980-12-01), Aichelmann
patent: 4328566 (1982-05-01), Thaler

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