Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-03-27
1999-06-01
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Testing
365200, 36523003, G11C 700
Patent
active
059094044
ABSTRACT:
A method for testing a memory device which statistically characterizes the failure time for a subset of cells sampled from the memory array before performing testing of the memory array in general. The memory device includes a testing unit which determines the failure times for cells in the sample subset, and a parameter calculation unit which computes one or more statistical parameters from the failure times. These statistical parameters are then used to determine a refresh pause time which is used in a data retention test of the memory array. The testing method may be performed when power is applied to the memory device. Thus, the BIST method may provide for the accurate detection of memory faults in the memory array at any power-up temperature. In addition, the testing method may be performed after the memory array attains an operational temperature, or in response to an operating system command.
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Kivlin B. Noel
Le Vu A.
LSI Logic Corporation
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