Refresh period generating circuit

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S211000, C365S233100

Reexamination Certificate

active

11180552

ABSTRACT:
A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature; and a selector which switches and selects among division outputs with respective frequencies from the dividing circuit based on an output of the temperature detector, and outputs a signal as a reference of the refresh period. The temperature dependence in the oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of the predetermined temperature range. The selector switches the division outputs out of the predetermined temperature range.

REFERENCES:
patent: 5752011 (1998-05-01), Thomas et al.
patent: 2005/0146964 (2005-07-01), Sako
patent: 05-307882 (1993-11-01), None
patent: 2002-215258 (2002-07-01), None

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