Refresh operations for semiconductor memory

Details Refresh operations for semiconductor memory Refresh operations for semiconductor memory

1980-02-11

1981-10-06

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 700

Patent

active

042939321

ABSTRACT:
A random access read/write MOS memory device employs an array of rows and columns of dynamic memory cells which are accessed by multiplexed row and column addresses latched in by row address strobe and column address strobe signals. For refresh operations, only the row address is needed, so no column address strobe occurs. During long periods of refresh-only operations, deterioration of internal clocks based on the column address strobe signal is avoided by boosting these clocks from the row address strobe signal.

REFERENCES:
patent: 3778784 (1973-12-01), Karp et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4207618 (1980-06-01), White et al.

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