Refresh operation type semiconductor memory device capable...

Details Refresh operation type semiconductor memory device capable... Refresh operation type semiconductor memory device capable...

2006-08-29

2006-08-29

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

07099222

ABSTRACT:
In a semiconductor memory device incorporating a memory core circuit requiring a refresh operation, a clock signal modifying circuit receives an external clock signal to generate a modified clock signal which is ineffective from a timing when the control is switched from an active mode to a special mode to a timing when at least one clock pulse time period of the external clock signal has passed after the control is switched from said special mode to an active mode. A forced refresh request signal generating circuit generates a forced refresh request signal at predetermined time periods and an internal clock signal having the same period as said forced refresh request signal. An all-time refresh request signal generating circuit generates an all-time refresh request signal in synchronization with the modified clock signal and the internal clock signal. A multiplexer selects the forced refresh request signal in the special mode and selects the all-time refresh request signal in the actual mode. A refresh pulse generating circuit generates a refresh pulse signal in accordance with one of the forced refresh request signal and the all-time refresh request signal selected by the multiplexer and transmits the refresh pulse signal to the memory core circuit. A read/write pulse generating circuit generates a read/write pulse signal in synchronization with the modified clock signal and transmits the read/write pulse signal to the memory core circuit.

REFERENCES:
patent: 4207618 (1980-06-01), White et al.
patent: 4748627 (1988-05-01), Ohsawa
patent: 4935900 (1990-06-01), Ohsawa
patent: 2006/0039220 (2006-02-01), Takahashi et al.
patent: 2006/0067151 (2006-03-01), Miyamoto
patent: 2001-210074 (2001-08-01), None
patent: 2002-074944 (2002-03-01), None

Affiliated with

Also associated with

Rating

Refresh operation type semiconductor memory device capable... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Refresh operation type semiconductor memory device capable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Refresh operation type semiconductor memory device capable... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3669745