Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-08-22
2006-08-22
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S201000, C365S225700, C365S233100, C365S189120
Reexamination Certificate
active
07095669
ABSTRACT:
Methods and circuit configurations for utilizing memory cells having weak retention times are provided. For some embodiments, rows identified as having weak retention cells may be refreshed more often than “normal retention” cells. As an example, if a normal refresh period is TREF, weak retention cells may be refreshed every TREF/2 or TREF/4 (possibly depending on the actual measured retention time).
REFERENCES:
patent: 5148546 (1992-09-01), Blodgett
patent: 5329490 (1994-07-01), Murotani
patent: 5629898 (1997-05-01), Idei et al.
patent: 5654913 (1997-08-01), Fukushima et al.
patent: 0 790 620 (1997-08-01), None
patent: WO96/28825 (1996-09-01), None
PCT International Search Report dated Feb. 14, 2005.
PCT Written Opinion dated Feb. 14, 2005.
Infineon - Technologies AG
Patterson & Sheridan L.L.P.
Tran Andrew Q.
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