Refresh cycle minimizer in a dynamic semiconductor memory

Details Refresh cycle minimizer in a dynamic semiconductor memory Refresh cycle minimizer in a dynamic semiconductor memory

1978-11-15

1981-09-29

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 800

Patent

active

042926769

ABSTRACT:
A refresh circuit for a dynamic semiconductor memory wherein each access to the main semiconductor memory for the storage or retrieval of information is detected and recorded in an auxiliary memory. During each memory access, the memory row being accessed is automatically refreshed as part of the storage or retrieval process. In accordance with the invention, the auxiliary memory is examined prior to the commencement of a refresh cycle and if a particular row in the main memory has been accessed during the current refresh cycle, that row is not refreshed but is skipped until the next refresh cycle, at which time the need for a refresh signal is again determined.

REFERENCES:
patent: 3760379 (1973-09-01), Nibby et al.
patent: 3810129 (1974-05-01), Behman et al.
patent: 3858184 (1974-12-01), De Vries
Johnson, Self-Actuating Refresh Scheme for Dynamic Memories, IBM Tech. Disc. Bul., vol. 20, No. 11A, 4/78, pp. 4399-4400.

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