Refresh counter circuit and control method for refresh...

Details Refresh counter circuit and control method for refresh... Refresh counter circuit and control method for refresh...

2006-11-28

2006-11-28

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S230080, C365S230090, C711S209000

Reexamination Certificate

active

07142476

ABSTRACT:
A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, including; n-stage counter which generates the row address corresponding to an address space of the normal area represented by n bits and the parity area represented by m (m<n) bits; an area discriminating circuit which generates an area discriminating signal; a first switching circuit for switching between a first connected state in which all stages of the counter are connected and a second connected state in which a n−m bits counter portion is disconnected from the counter; and an automatic reset circuit which generates a reset signal so that the count operation in the normal area is discriminated by the discriminating signal when stopping of the refresh operation in the second connected state.

REFERENCES:
patent: 5999473 (1999-12-01), Harrington et al.
patent: 6134168 (2000-10-01), Harrington et al.
patent: 6795362 (2004-09-01), Nakai et al.
patent: 7017027 (2006-03-01), Inaba et al.
patent: 20004-118938 (2004-04-01), None

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