Refresh counter

Details Refresh counter Refresh counter

1979-08-13

1981-10-20

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 1140

Patent

active

042964806

ABSTRACT:
A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.

REFERENCES:
patent: 3796998 (1974-03-01), Appelt
patent: 3806898 (1974-04-01), Askin
patent: 3858185 (1974-12-01), Reed
patent: 4028557 (1977-06-01), Wilson
patent: 4079462 (1978-03-01), Koo

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