Refresh controller with low peak current

Details Refresh controller with low peak current Refresh controller with low peak current

2006-04-18

2006-04-18

Eckert, George (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050, C365S230080, C365S230030, C365S076000, C365S093000, C365S194000

Reexamination Certificate

active

07031216

ABSTRACT:
The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable signal and a second bank enable signal. The present invention has an advantage that there is no problem of substantially reducing a refresh prosecution time for a second portion because a delayed refresh enable signal is being disabled even while the second bank enable signal is being enabled.

REFERENCES:
patent: 6333886 (2001-12-01), Cho et al.
patent: 6518595 (2003-02-01), Lee
patent: 6621753 (2003-09-01), Fujimoto et al.
patent: 6847572 (2005-01-01), Lee et al.

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