Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-10-01
2004-09-21
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S195000
Reexamination Certificate
active
06795363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device which requires refresh operation and a refresh control method, and particularly to a semiconductor memory device which can control the refresh operation on the occasion of executing the refresh operation as an internal access operation independent of an external access operation and a refresh control method.
2. Description of Related Art
A semiconductor memory device represented by a dynamic random access memory (hereinafter referred to as DRAM) is required to periodically perform the refresh operation in order to maintain the data stored in a memory cell.
FIG. 10
shows operation waveforms in the so-called self-refresh operation which means the automatic refresh operation executed in every predetermined period in the standby state among the ordinary refresh operations in the related art. FIG.
10
(A) indicates the control in the case of the asynchronous DRAM in which the self-refresh operation is executed in the CAS before RAS refresh operation. Namely, the self-refresh operation is controlled, for the external control signals /RAS and /CAS, with a signal transition sequence opposed to that of the ordinary access operation in which the /CAS signal is transitioned to a low logic level before the low logic level transition of the /RAS signal. The state of self-refresh operation can be maintained while the external control signals /RAS, /CAS are in the low logic level. Moreover, FIG.
10
(B) indicates the control in the case of the synchronous DRAM (hereinafter referred to as SDRAM) in which the self-refresh operation is executed with a command input synchronized with a clock signal CLK. The self-refresh operation is started with a start command REF of the refresh operation and thereafter the self-refresh state is maintained. When a command EXIT is issued, the self-refresh state is canceled.
During the period of the self-refresh operation, an external access operation such as read and write of data is never conducted ((I) of
FIG. 10
) and the refresh operation as the internal access operation is continued. A count-up signal COUNT of a refresh address counter is outputted to a refresh-operation-start request signal REQ (I) which is outputted in the predetermined refresh period and a refresh address signal Add (C) is sequentially incremented. Thereafter, a refresh executing signal is outputted based on the refresh-operation-start request signal REQ (I) and the refresh operation is sequentially executed to the memory cell areas (memory cells connected to the predetermined word lines) indicated with the refresh address signal Add (C).
An ordinary self-refresh operation in the related art explained above is always controlled with the external control signals /RAS, /CAS or with the external commands REF, EXIT exclusive of the external access operation such as data read and write operations. Therefore, during the self-refresh operation period, the refresh-operation-start request signal REQ (I), count-up signal COUNT, refresh address signal Add (C) and refresh executing signal are respectively corresponding to each other on 1:1 basis and the address areas indicated by the refresh address signal Add(C) which is sequentially incremented in every refresh period is then sequentially selected.
In recent years, as a result of diversification of the functions required for the mobile devices with the rapid development thereof, the static random access memory (hereinafter referred to as SRAM) which has been loaded to the predecessors is now replaced with further large capacity memory. Therefore, from the necessity to load a large capacity memory explained above in the practical price in the limited space, a DRAM with built-in refresh function which is so-called a pseudo SRAM has been used. That is, a pseudo SRAM for controlling the refresh operation peculiar to the memory cell of DRAM or the like which assures high integration density and low bit price is built-in. Moreover, as a means to realize a synchronous SRAM (hereinafter referred to as SSRAM) with a memory cell of SDRAM for the requirement of high speed operation in future, the specification for the pseudo SSRAM has become a practical means in current.
Since the pseudo SRAM or pseudo SSRAM assures compatibility with SRAM or SSRAM in the circuit operations, it is specified to automatically execute the refresh operation whenever it is required. Therefore, the refresh operation as the internal access operation and an ordinary data read/write operation as the external access operation are executed independently in the desired timing.
FIG. 11
shows waveforms in the external access operation and the refresh operation of the pseudo SRAM in the related art. Since the refresh operation as the internal access operation is executed independent of the read/write operation as the external access operation, arbitration is required when both operations are overlapped. (II) of
FIG. 11
indicates the overlap of the single refresh operation and external access operation. An external-access-start request signal REQ (O) is outputted with a delay from a refresh-operation-start request signal REQ (I). When the single refresh operation and single external access operation are overlapped, arbitration of access operation is conducted to execute any one single operation with a priority and then execute later the other single operation with a certain delay. In
FIG. 11
, the refresh operation for the refresh address #
1
is executed with the priority and thereafter the external access operation is conducted for the address #b. The refresh operation is executed without any delay to the refresh-operation-start request signal REQ (I). Meanwhile, the external access operation is executed with a certain delay from the external-access-start request signal REQ (O).
(III) of
FIG. 11
indicates the external successive access operation such as a page operation to be executed bridging over the refresh operation. The refresh-operation-start request signal REQ (I) is issued during the period of the continuous external-access-start request signal REQ (O). In general, since a high speed continuous access operation is required in the external successive access operation, execution of the refresh operation is inhibited until such continuous operation is completed and the arbitration is conducted to execute the refresh operation following the completion of the external successive access operation. The external successive access operation is executed with priority for the addresses #c to #c+k and thereafter the refresh operation is executed for the refresh address #
3
. The external successive access operation is executed without delay for the external-access-start request signal REQ (O). On the contrary, the refresh operation is executed with a delay from the refresh-operation-start request signal REQ (I).
Moreover, a mobile device is often placed under the standby state for a longer period such as a mobile phone and a digital camera, etc. and therefore this mobile device is always required to reduce the current dissipation up to the ultimate extent in the standby state in order to improve the continuous duration time characteristic while the device is operated with a battery. Therefore, it is an essential matter for a DRAM or the like to reduce the current dissipation in the refresh operation such as the self-refresh operation which is periodically conducted even during the standby state. As a method to reduce the current dissipation during the refresh operation, two kinds of methods, one is the refresh-thinning-out operation and the other is the partial refresh operation, have been proposed.
FIG. 12
shows the waveforms in the refresh operation corresponding to the refresh-thinning-out operation. In the case of the memory cells loaded to a semiconductor memory device, its electrical characteristic is generally given a predetermined width. The data holding characteristic stored in the memory cells also has a predetermined width and the r
Higashiho Mitsuhiro
Nakashima Masami
Arent Fox
Auduong Gene N.
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