Refresh control for semiconductor memory device

Details Refresh control for semiconductor memory device Refresh control for semiconductor memory device

2005-06-07

2005-06-07

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S230080

Reexamination Certificate

active

06903990

ABSTRACT:
An external access timing signal becomes active according to changes of the external address. An address latch signal becomes active according to the timing when the external access timing signal becomes active. In a case where the changes of the external address occurs while the address latch signal is active and consequently the external access timing signal becomes active, a refresh arbiter signal does not become active. When the refresh arbiter signal becomes active after the generation of the refresh timing signal, a refresh execution timing signal becomes active according to the change of the refresh arbiter signal. The time period when the address latch signal is active is set to be substantially the same as the preferable activation time period. The time period when the external access timing signal is active is set to be substantially the same as the preferable pre-charge time period.

REFERENCES:
patent: 6336180 (2002-01-01), Long et al.
patent: 6421754 (2002-07-01), Kau et al.
patent: 6597615 (2003-07-01), Mizugaki
patent: 6789210 (2004-09-01), Satoh et al.
patent: A-2002-74945 (2002-03-01), None

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