Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-08-02
2004-07-20
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230060, C365S236000
Reexamination Certificate
active
06765838
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a configuration of a refresh control circuitry for restoring storage data of dynamic type memory cells in prescribed periods for retention of the storage data. More specifically, the present invention relates to a configuration for reducing current consumption in a self-refresh mode where storage data of a memory cell is internally refreshed periodically.
2. Description of the Background Art
Semiconductor memory devices include a dynamic random access memory (DRAM) storing information in a capacitor in an electrical charge form. A DRAM cell is normally formed of an access transistor and a capacitor. Compared to a static random access memory (SRAM) cell, a unit memory cell of the DRAM is low in cost per bit, and small in layout area and in the number of components thereof Therefore, the DRAM can implement a memory device with small occupying area and large storage capacity at a low price, so that DRAMs are widely used in a variety of applications, such as a main memory.
A DRAM cell stores information in an electrical charge form in a capacitor, as described above. Inevitably, there is a possibility that the stored information would be lost due to a leakage current at the capacitor. In order to retain the stored information, refreshing is performed, in which data stored in a memory cell is read out and rewritten periodically. There are two operation modes for carrying out the refresh. One is an auto-refresh mode, in which a refresh address is internally produced to refresh the storage data at an address designated by the refresh address according to an externally supplied refresh instruction, in a normal operation mode during which data access is performed. The other is a self-refresh mode, in which the refresh is carried out by internally generating a refresh execution timing and a refresh address. The self-refresh mode is set, for example, in a sleep mode in which no data access is made to the DRAM over a relatively long period of time. In this self-refresh mode, the DRAM is required only to retain data.
If a DRAM is applied to battery-driven equipment such as portable equipment, the current consumption should be limited to a minimum level to elongate the life of the battery. Especially in the self-refresh mode with the entire equipment being in standby, the current consumption should be made as small as possible. In the self-refresh mode, row selection of memory cells and reading/rewriting of memory cell data are performed according to a refresh address. Thus, a current is consumed in the self-refresh mode in execution of the refresh operation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device permitting considerable reduction of current consumption in a self-refresh mode without a complicated circuit configuration.
The semiconductor device according to the present invention includes refresh address generating circuitry for generating a multi-bit refresh address designating a memory cell to be refreshed, and refresh activating circuitry for generating a refresh array activating signal for activating a refresh operation in accordance with a specific address bit of the refresh address and a refresh request.
In the refresh mode, when the specific address bit of the refresh address is in a specific state, the refresh request is invalidated so as to lengthen a refresh interval without a change of a period of an issuance of the refresh request by the timer. Accordingly, the number of times of refresh per unit time in the self-refresh mode, and hence, current consumption in the self-refresh mode can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5243576 (1993-09-01), Ishikawa
patent: 5446695 (1995-08-01), Douse et al.
patent: 5877978 (1999-03-01), Morishita et al.
patent: 5969981 (1999-10-01), Kono
patent: 6307776 (2001-10-01), So et al.
patent: 6542425 (2003-04-01), Nam
Matsumoto Junko
Okamoto Takeo
Yamauchi Tadaaki
Auduong Gene
McDermott & Will & Emery
Renesas Technology Corp.
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