Static information storage and retrieval – Read/write circuit – Signals
Patent
1991-07-19
1993-04-27
Clawson, Jr., Joseph E.
Static information storage and retrieval
Read/write circuit
Signals
365222, 365233, 307592, 307596, 307602, 307606, G11C 700
Patent
active
052068307
ABSTRACT:
A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.
REFERENCES:
patent: 4578782 (1986-03-01), Kraft et al.
patent: 4809233 (1989-02-01), Takemae
patent: 4837466 (1989-06-01), Kanauchi
patent: 5075886 (1991-12-01), Isobe et al.
Isobe Mitsuo
Ueno Hisashi
Clawson Jr. Joseph E.
Kabushiki Kaisha Toshiba
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