Refresh control circuit for memory

Details Refresh control circuit for memory Refresh control circuit for memory

1991-09-04

1994-06-21

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

36523002, 365233, G11C 700

Patent

active

053233522

ABSTRACT:
A refresh control circuit includes a refresh request generating circuit, a multiplexer, a memory access control circuit and an elimination control circuit. The refresh request generating circuit periodically outputs a transfer pulse and a refresh packet for refreshing. The merging control circuit receives a transfer pulse for normal access and a transfer pulse for refreshing. The merging control circuit, when the transfer pulse for refreshing and the transfer pulse for normal access contend with each other, applies first the transfer pulse to the memory access control circuit, makes the other stand by and generates an identification signal for identifying normal access and refreshing. The multiplexer receives a refresh packet and a data packet and applies one of the packets to the memory access control circuit in response to the identification signal. The memory access control circuit selectively controls a normal access operation based on the data packet or a refresh operation based on the refresh packet in response to the identification signal to output a transfer pulse. When an identification signal indicates a refresh operation, the elimination control circuit eliminates a transfer pulse output from the memory access control circuit.

REFERENCES:
patent: 4334295 (1982-01-01), Nagami
patent: 4344157 (1982-08-01), White, Jr. et al.
patent: 4677592 (1987-06-01), Sakurai et al.
patent: 4829484 (1989-05-01), Arimoto et al.

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