Refresh control circuit for low-power SRAM applications

Details Refresh control circuit for low-power SRAM applications Refresh control circuit for low-power SRAM applications

2001-01-22

2002-08-13

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S156000, C365S226000

Reexamination Certificate

active

06434076

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory systems, and more specifically, a low power static random access memory (SRAM) system including a power management scheme implementing a novel, robust refresh control circuit for enabling significantly reduced low power operation.
2. Discussion of the Prior Art
SRAM, or static random access memory, due to its high-performance nature, is widely used in computer systems. As the density of the SRAM is further improved along with the scaling of the technology, the SRAM memory chips, or embedded macros are also widely adopted in the hand-held systems, such as cell phone, personal digital assistants (PDA), global positioning systems (GPS), especially for L
1
or L
2
cache. The design of SRAM is simpler than that of dynamic random access memory (DRAM) systems in that the data stored in the array are latched in the cells and no refresh is required. SRAM is additionally faster than DRAM, since all the read operations are nondestructive, no write back or bit-line pre-charge period is required. Recently, a 4-T SRAM cell has been proposed by NEC to further reduce the SRAM size. Normally, SRAM cell efficiency (i.e., the area ratio of array to the whole chip) is higher than that of DRAM. Area overhead such as on-chip generator system, refresh unit, redundancy and complex BIST are absent from SRAM circuits.
However, the biggest concern for SRAMs to be used for low-power systems is the stand-by current from the arrays when they are idle. The power supply to the SRAM array must be maintained during the low-power modes, e.g., sleep and stand-by modes, or otherwise, the data stored in the array will be lost. Some prior art systems have addressed this problem by shutting off the portion of the array that is not in use. This method relies on the system to decide which part of the array is in use, and to switch off the array that is not needed in the low-power mode. This also requires a large area for placing the switch device, since every row needs a switch to selectively turn it off. As proposed by M. Powell, from Purdue University in the digest paper entitled “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep Sub-Micron Cache Memory” published by the International Symposium on Low-Power Electronic Design (ILPED 2000 pages 90-95), a switch to shut off the row may degrade the SRAM performance if it is not properly sized. Additionally, a complex decoding and switch circuit to shut off the rows is required. This approach is especially not effective when a small SRAM is used, and when most of the array is needed for data storage during the low-power mode, e.g., when SRAMs are to be used for cache applications.
The concept of low-power SRAM using a refreshable array scheme has been proposed. The power saving of the refreshable SRAM array during stand-by is significant, especially when the array is large and stand-by period is long. Use of a conventional DRAM-like refresh circuit that is able to perform the refreshing of local supplies, and SRAM cells, is not very desirable in that such a solution is typically (1) bulky in size, (2) consumes a larger power overhead, and (3) requires an initial test to set the refresh timing.
It would be highly desirable to provide a power management circuit to minimize the power consumption of SRAM arrays especially during the low-power modes of operation.
It would be further highly desirable to provide a new and robust refresh circuit that is relatively smaller than those implemented in DRAM circuits, and that obviates the need of conventional clock generator for the refresh timing.
It would be further highly desirable to provide a new and robust refresh circuit that where the refresh timing is generated directly from the internal or local voltage supply.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power management circuit to minimize the power consumption of SRAM arrays especially during the low-power mode.
It is a further object of the present invention to implement a refresh timing circuit similar to that of DRAMs to conduct refresh to the internal (local) voltage supply of the SRAM arrays, however implements a novel refresh timing mechanism that is generated directly from the local voltage supply.
According to the principles of the invention, there is provided a power management circuit for an SRAM system including one or more memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to each local power supply during active mode of operation, the power management circuit comprising: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory cell refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode, wherein, during the low power mode, the refresh circuit intentionally enables the local power supply to float and drift to a lower predetermined voltage level prior to the memory cell refresh operation.
In a further embodiment, there is implemented a refresh timing circuit similar to that provided in DRAM circuits to conduct refresh to the local power supply of the SRAM arrays. Particularly, in accomplishing improved low power operation, a soft-refresh to the SRAM arrays and the local power supply is implemented. The SRAM arrays are further partitioned into multiple of sub-arrays with ground buses used to isolate the sub-arrays. To optimize the power saving, a test algorithm is proposed to determine the optimum SRAM array refresh cycle time which is programmable by fuse elements in the power management circuit.
Advantageously, detrimental noise coupling effects are avoided while SRAM arrays are in the low-power mode to prevent the possibility of lost data.


REFERENCES:
patent: 5047987 (1991-09-01), Kosuge
patent: 5204840 (1993-04-01), Mazur
patent: 5428252 (1995-06-01), Walker

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