Refresh control circuit for ICs with a memory array

Details Refresh control circuit for ICs with a memory array Refresh control circuit for ICs with a memory array

2006-02-21

2006-02-21

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230040

Reexamination Certificate

active

07002867

ABSTRACT:
An IC having an array of memory cells that can be accessed through two different ports is described. Read/write operation is performed through one of the ports. The refresh of the memory cell is performed through the other port. In one embodiment, the other port is only used internally to the memory array.

REFERENCES:
patent: 5923593 (1999-07-01), Hsu et al.
patent: 6359813 (2002-03-01), Uchida et al.
patent: 6445638 (2002-09-01), Hsu et al.
patent: 6552951 (2003-04-01), Raj et al.
patent: 2001/0012230 (2001-08-01), Takemae et al.
patent: 2001/0017791 (2001-08-01), Funyu et al.
patent: 2002/0057617 (2002-05-01), Afghahi et al.
patent: WO 00/19437 (1999-09-01), None
Sakurai et al., “Transparent-Refresh DRAM (TReD) Using Dual-Port DRAM Cell”, IEEE 1998 Custom Integrated Circuits Conference, May 16-19, 1998, p. 4.3.1-4.3.4, Rochester, New York.

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