Refresh control circuit and method for multi-bank structure...

Details Refresh control circuit and method for multi-bank structure... Refresh control circuit and method for multi-bank structure...

2006-12-05

2006-12-05

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000, C365S230030

Reexamination Certificate

active

07145827

ABSTRACT:
A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal and a reference signal; and a bank selection unit for generating a plurality of bank selection signals in response to the plurality of bank number signals and a piled-refresh control signals to thereby refresh the plurality of banks.

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patent: 6859407 (2005-02-01), Suh
patent: 2003/68073 (2003-03-01), None
patent: 2003/242800 (2003-08-01), None

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