Refresh control circuit

Details Refresh control circuit Refresh control circuit

1999-02-16

2000-10-31

Zarabian, Amir

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 700

Patent

active

061412791

ABSTRACT:
A refresh control circuit is provided that includes a control signal latency setting circuit that sets a control signal (CAS) latency, and a refresh mode setting that receives an output signal (REF) from the auto refresh mode decoder and an output signal (SREF) from the self-refresh mode decoder and outputs an output signal.

REFERENCES:
patent: 4758992 (1988-07-01), Taguchi
patent: 5347491 (1994-09-01), Kagami
patent: 5365487 (1994-11-01), Patel et al.
patent: 5999481 (1999-12-01), Cowles et al.

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