Refresh control circuit

Details Refresh control circuit Refresh control circuit

1990-02-06

1992-02-18

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 395425, 364DIG1, G11C 700, G11C 800

Patent

active

050899872

ABSTRACT:
A refresh control circuit for a processor which is connected to dynamic random access memory via an address bus, a data bus and control signal lines. A refresh control signal is output at predetermined intervals to refresh the dynamic random access memory. The refresh control circuit includes control circuitry and an address generator. The address generator latches a value received from the control circuitry. Based on such latched value, a refresh address is changed by the N-th power of 2, N corresponding to the number of memory banks of the dynamic random access memory.

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Official Announcement Publn. Nippon Denki Databook Bulletin "V-Series Microprocessor/Periphery".
NEC Corporation, V Series Microprocessor/Peripheral, Data Book, 1987, Apr. 1, 1987, pp. 306-434.

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