Refresh circuit for SDRAM

Details Refresh circuit for SDRAM Refresh circuit for SDRAM

1999-08-25

2000-11-07

Zarabian, Amir

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 700

Patent

active

06144605&

ABSTRACT:
The refresh circuit for the SDRAM includes: a control signal input buffer for synchronizing externally inputted signals and a column operation control signal (DQM) with a predetermined clock signal and outputting resultant signals; a command generating unit for generating a first refresh command or a second refresh command by receiving a logic combination signal of the signals supplied from the control signal input buffer in accordance with the column operation control signal; a row activating unit for generating a control signal to activate a row operation in accordance with the first refresh command or the second refresh command; a row activation controlling unit for controlling the row activating unit; an internal address counter for generating a predetermined internal address in accordance with the first refresh command; an external address path for receiving an address of a wordline to be refreshed; a row pre-decoder for receiving the internal address from the internal address counter or the external address supplied via the external address path and decoding the received signal to a row address signal of a predetermined bit; a wordline model signal generating unit for generating a wordline model signal when an actual wordline is selected in accordance with the first or second refresh command; and a sense amp state predicting unit for generating a predetermined signal which indicates a sensing degree of a sense amp after a predetermined time has elapsed from a point when the wordline model signal is inputted.

REFERENCES:
patent: 5862093 (1999-01-01), Sakakibara

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