Refresh circuit for DRAM with three-transistor type memory cells

Details Refresh circuit for DRAM with three-transistor type memory cells Refresh circuit for DRAM with three-transistor type memory cells

1997-07-29

1998-09-22

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365187, 365188, 365149, 365150, 36523005, G11C 700

Patent

active

058124764

ABSTRACT:
A semiconductor memory device of a three-transistor cell type dynamic random-access memory with improved performances includes a circuit arranged between a write bit line and a read bit line. During a read operation, the circuit generates a voltage difference responsive to information that is stored in the memory cell during a read operation. A latch-type sense amplifier amplifies and latches the voltage difference between the write bit line and the read bit line. When information is read from a memory cell, the information in the memory cell amplified by the latch-type sense amplifier is read through the read bit line while being written to the memory cell via the write bit line to refresh the information in the memory cell.

REFERENCES:
patent: 4935896 (1990-06-01), Matsumura et al.
patent: 5652728 (1997-07-01), Hosotani et al.
patent: 5710742 (1998-01-01), Carter et al.

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