Refresh arrangement in a block divided memory including a plural

Details Refresh arrangement in a block divided memory including a plural Refresh arrangement in a block divided memory including a plural

1988-05-11

1990-04-03

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518912, 365222, 36523003, G11C 700

Patent

active

049146300

ABSTRACT:
In a block access memory, the memory cell array is divided into a plurality of blocks, one word line is selected based on the external address and the access to the memory cells connected thereto is carried out in one block and, simultaneously, one word line is selected based on the internally generated refresh address and the refresh of the memory cells connected to the word line is carried out in the other block.

REFERENCES:
patent: 4044339 (1977-08-01), Berg
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4486860 (1984-12-01), Takemae et al.
patent: 4541075 (1985-09-01), Dill et al.
patent: 4680738 (1987-07-01), Tam
patent: 4725987 (1988-02-01), Cates
patent: 4758993 (1988-07-01), Takemae
IEEE J. of Sol. St. Circuits: "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications", by Raymond Pinkham et al., vol. SC-19, No. 6, Dec. 1984, pp. 999-1007.

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