Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1987-03-24
1989-02-21
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
365201, 365189, G11C 700, G11C 1140
Patent
active
048071960
ABSTRACT:
A semiconductor memory system with a fully automated built-in refresh control circuitry, comprising a dynamic random access memory cell array, a data transfer gate circuit through which data signals are to be transferred to or from the memory cell array, a data transfer request signal generator to produce a signal requesting activation of the gate circuit, a refresh request signal generator to produce a signal to request refreshing of the memory cell array, a refresh address counter for storing an address signal representing a memory address where the memory cell array is to be refreshed, and a refresh test control circuit responsive to the signals produced by the data transfer request and refresh request signal generators and operative to produce from the signal from the data transfer request signal generator a control signal to check the refresh address counter for proper operation during a refresh test cycle which is initiated by a signal supplied from an external source.
REFERENCES:
patent: 4453237 (1984-06-01), Reese et al.
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4691303 (1987-09-01), Churchward et al.
Bowler Alyssa H.
Fears Terrell W.
NEC Corporation
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