Reflected interrupt for hardware-based encryption

Details Reflected interrupt for hardware-based encryption Reflected interrupt for hardware-based encryption

2005-06-21

2005-06-21

Barron, Gilberto (Department: 2132)

Electrical computers and digital processing systems: support

Data processing protection using cryptography

Computer instruction/address encryption

C713S191000, C713S192000, C713S160000, C380S239000, C370S235000

Reexamination Certificate

active

06910133

ABSTRACT:
A router may induce a reflected interrupt to indicate to a processor in the router to execute encryption or decryption commands on packets in an input queue. The reflected interrupt may have a lower priority than interrupts generated for the processing of time-critical packets. This prevents starvation of potentially important packets while still providing for the security of a critical section for encryption and decryption commands. The router may also be designed to detect when a predefined event occurs and stop the execution of encryption or decryption commands accordingly. This is especially useful for preventing the starvation of lower priority packets, as the encryption or decryption processing loop may be stopped intermittently to allow the processor to perform other tasks. Scheduling of the encryption or decryption process may also help prevent traffic-related problems.

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