Reference voltage generator and method utilizing clamping

Details Reference voltage generator and method utilizing clamping Reference voltage generator and method utilizing clamping

1996-04-22

1998-07-21

Wong, Peter S.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323314, 323907, 327537, G05F 316

Patent

active

057839352

ABSTRACT:
A reference voltage generating circuit has a divider circuit for decreasing a received external power-supply voltage and for providing the decreased voltage at a reference voltage output terminal. A PMOS transistor clamps the reference voltage at a predetermined voltage level, one end thereof being coupled to the reference voltage output terminal and the other end being coupled to a ground. A compensating unit adjusts the substrate voltage of the PMOS transistor to compensate for level variations of the reference voltage in response to the level variations. Thus, variations in the reference voltage caused by changes in processing variables are compensated, thereby maintaining the reference voltage at a predetermined level.

REFERENCES:
patent: 4095164 (1978-06-01), Ahmed
patent: 4368420 (1983-01-01), Kuo

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