Reference voltage generation for memory circuits

Details Reference voltage generation for memory circuits Reference voltage generation for memory circuits

2002-09-04

2004-02-03

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S210130

Reexamination Certificate

active

06687150

ABSTRACT:

BACKGROUND OF INVENTION
Ferroclectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semi conductor memory devices.
FIG. 1
shows a conventional ferroelectric memory cell
105
having a transistor
130
and a ferroelectric capacitor
140
. A capacitor electrode
142
is coupled to a plateline
170
and another capacitor electrode
141
is coupled to the transistor which selectively couples or decouples the capacitor from a bitline
150
, depending on the state (active or inactive) of a wordline
160
coupled to the transistor gate. A plurality of memory cells are interconnected via wordlines and bitlines to form an array. Sense amplifiers are coupled to the bitlines to access the memory cell.
Information is stored in the capacitor as remanent polarization. When a memory cell is read, a read signal is produced on the bitline. The read signal voltage is either V
HI
or V
LO
, depending on whether a logic 1 or logic 0 is stored in the memory cell. The read signal is compared with a reference voltage by the sense amplifier and amplified. The reference voltage is set to a level between V
LO
and V
HI
(sensing window). Typically, V
LO
is about 0.6V and V
HI
is about 1.2V for ICs with operating voltages of about 2.5V.
The reference voltage can be generated through the use of a reference cell scheme. Typically, a reference cell is provided for each bitline and pre-biased to produce the reference voltage. A reference cell is similar to a memory cell except that it is coupled to a reference wordline and a reference plateline. Pre-biasing is performed by, for example, writing a “0” to the reference cell to produce the reference charge which is subsequently shared with the opposite BL from that receiving the cell signal (e.g., non-switching read of “0”). The size of the reference cell should be chosen to produce a higher cell capacitance compared to the regular memory cell. This is because the reference signal (“0” signal of the reference cell) should be between the “0” and “1” signals of the actual memory cell.
The read signal is compared with the reference voltage produced by the reference cell on the reference bitline. Generally, the read signals are distributed over a voltage range (distribution), as shown in FIG.
2
. This may be due to various reasons, such as process variations or difference in bitline capacitances experienced by different cells. The reference voltage
266
is selected to be between the logic 0 and logic 1 read signal distributions
204
and
206
to provide the optimum sensing window
294
.
Like the memory cells of the array, the charge generated by the reference cells will also be distributed within a range
268
. Having a reference signal distribution effectively reduces the sensing window. For example, the logic 1 signal sensing window
296
is effectively reduced to between the end of the reference cell;distribution and beginning of the logic 1read signal distribution (
298
). This may cause failures in sensing, particularly with future designs having smaller sensing window due to a reduction in operating voltages.
To reduce the variations between the different reference cells, the reference cells.
314
0
−
314
n−1
of an array having n number of bitlines BL
0
−BL
n−1
are interconnected by a conductive line
378
between the reference cell transistor
374
and capacitor
376
, as shown in FIG.
3
. Interconnecting all the reference cells in the array is described in, for example, Kang et al., “A Pulse-Tuned Charge Controlling Scheme for Uniform Main and Reference Bitline Voltage Generation on 1T1C FeRAM”, Symp on VLSI Circuits Digest, p. 125, June 2001, which is herein incorporated by reference for all purposes. However, in such a scheme, a failure in one reference cell would result in failure of the whole array.
From the foregoing discussion, it is desirable to provide an improved reference cell scheme which reduces the distribution of reference cell charge.
SUMMARY OF INVENTION
The invention relates to memory integrated circuits (ICs), and more particularly, to reference voltage generation in memory ICs. In one embodiment, the memory IC includes a memory block having a plurality of memory cells. The memory cells are interconnected in a first direction by wordlines and bitlines in a second direction. A plurality of memory cells are provided for the memory block. A bitline includes a reference cell. In one embodiment, the bitlines of the memory block are separated into groups, wherein at least some of the reference cells within a group are interconnected to average out the reference cell charge variations. Averaging out the reference cell charge variations produces a narrower reference voltage distribution, which increases the sensing window. This improves reliability and increases manufacturing yield.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1
shows a conventional ferroelectric capacitor;
FIG. 2
shows read signal distributions in a conventional ferroelectric memory array;
FIG. 3
shows a conventional reference cell scheme;
FIG. 4
shows a reference cell scheme in accordance with one embodiment of the invention; and
FIG. 5
shows a reference cell distribution in accordance with one embodiment of the invention.


REFERENCES:
patent: 6246621 (2001-06-01), Miyamoto
patent: 6333870 (2001-12-01), Kang
patent: 10209387 (2002-04-01), None

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