Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-02-28
2004-03-16
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S196000, C365S205000, C365S210130, C365S226000
Reexamination Certificate
active
06707725
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to Japanese Patent Application Number 2001-057499 filed Mar. 1, 2001, the content of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as, for example, an electrically rewritable nonvolatile memory. In particular, the present invention relates to a reference voltage generation circuit used for a plurality of sense amplifiers for simultaneously reading information from a plurality of memory cells using a reference voltage obtained from a reference cell, a memory reading circuit including such a reference voltage generation circuit, and an electronic information device, such as, for example, a cellular phone or a computer using such a memory reading circuit.
2. Description of the Related Art
Conventionally, semiconductor memory devices such as, for example, EEPROMs (Electrically Erasable and Programmable Read Only Memories) and flash EEPROMs (hereinafter, referred to as the “flash memories”) are known as electrically rewritable nonvolatile memories. These semiconductor memory devices each include a sense amplifier circuit (sense amplifier) and circuits related thereto as a memory reading circuit for reading information memory cell transistors (hereinafter, referred to as “memory cells”).
An exemplary structure of a sense amplifier circuit and circuits related thereto is now described. In this example, a memory cell, from which the sense amplifier and the like read information, includes a stacking gate electrode, which is formed of polycrystalline silicon and has a two-layer structure of a control gate electrode and a floating gate electrode.
According to one operating principle of a memory cell having a stacking gate structure, information is stored based on whether the floating gate electrode is in a state of containing electrons or in a state of not containing electrons.
Herein, an operation for placing the floating gate electrode into a state of containing electrons will be referred to as a “writing operation”, and an operation for placing the floating gate electrode into a state of not containing electrons will be referred to as an “erasing operation”. The writing operation and the erasing operation will not be described in detail.
A memory cell in which the floating gate electrode is in the state of containing electrons (obtained by the writing operation) will be referred to as a “program cell”. A memory cell in which the floating gate electrode is in the state of not containing electrons (obtained by the erasing operation) will be referred to as an “erase cell”. When a voltage is applied to the control gate electrode and a bias voltage is applied to a source electrode and a drain electrode of each of the program cell and the erase cell, the amount of current flowing in the program cell is smaller than that in the erase cell. (The state in which the above-mentioned voltages are applied to the control gate electrode, the source electrode and the drain electrode will be referred to as a “memory cell reading condition”). The reason that the amount of current flowing in the program cell is smaller is because in accordance with whether the floating gate electrode contains electrons or not, the electric field intensity, applied to the channel region of the memory cell when a voltage is applied to the control gate electrode, changes, thus the amount of current flowing in the memory cell also changes. The electric field intensity, obtained when a voltage is applied to the control gate electrode, changes in accordance with the number of electrons existing in the floating gate electrode. In accordance with the electric field intensity, the amount of current changes as described above. Here, whether the floating gate electrode contains electrons or not indicates whether the number of electrons in the floating gate electrode is relatively large or small.
By the above-described principle, data value “0” is stored in a memory cell when the amount of current is small, and data value “1” is stored in a memory cell when the amount of current is large.
The sense amplifier circuit determines whether the amount of current flowing in each memory cell under the memory cell reading condition is small or large, and outputs data value “0” or data value “1” based on the determination result. The determination on whether the amount of current is small or large can be made with respect to the amount of a reference current. In this case, a transistor having a structure similar to that of the memory cells (hereinafter, referred to as a “reference cell”) can be used in order to produce the reference current. Such a transistor is produced so as to have the same influences of the temperature characteristics and voltage characteristics for reading memory cells as those of the memory cells.
The current amount of the reference cell can be an intermediate value between the current amount of the program cell and the current amount of the erase cell. The number of electrons in the floating gate electrode of the reference cell can be adjusted to be between the number of electrons in the floating gate electrode of the program cell and that of the erase cell.
FIG. 10
is a circuit configuration of a sense amplifier circuit
100
in a conventional flash memory. As shown in
FIG. 10
, the sense amplifier circuit
100
includes a memory cell section
101
including a selection circuit; a feedback-type current detection circuit
102
, which is connected to a drain electrode of a memory cell
101
b
for reading (reading memory cell
101
b
) through a selection transistor
101
a
of the selection circuit; a reference cell section
103
acting as a reference current generation circuit and having a structure similar to that of the reading memory cell
101
b
, the reference cell section
103
also including a selection circuit; a feedback-type current detection circuit
104
having a structure similar to that of the reading memory cell
101
b
and connected to a drain electrode of a reference cell
103
b
through a selection transistor
103
a
of the selection circuit; and a comparator circuit
105
for comparing a voltage output from the reading memory cell
101
b
and a voltage output from the reference cell
103
b.
The current detection circuits
102
and
104
each use a load circuit for performing current-voltage conversion in order to obtain a voltage, which is to be output to the comparator circuit
105
. Transistor loads
102
a
and
104
a
shown in FIG.
11
and resistance loads
102
b
and
104
b
shown in
FIG. 12
are examples of such a load circuit.
In order to perform a reading operation from the reading memory cell
101
b
, the sense amplifier circuit
100
shown in
FIG. 10
can include a charging circuit
106
for providing the drain electrode of the reading memory cell
101
b
with a bias voltage of the memory cell reading condition, and can also include a charging circuit
107
for providing the drain electrode of the reference cell
103
b
with a bias voltage of the memory cell reading condition.
With reference to
FIG. 10
, a reading operation performed on the conventional sense amplifier circuit
100
will be described.
As shown in
FIG. 10
, a gate voltage to be applied for performing the reading operation (hereinafter, referred to as a “reading gate voltage”) is applied to the control gate electrode of the reading memory cell
101
b
selected by the selection transistor
101
a
. Simultaneously, a drain voltage to be applied for performing the reading operation (hereinafter, referred to as a “reading drain voltage”) is applied to the drain electrode of the selected reading memory cell
101
b
through the selection transistor
101
a
by the charging circuit
106
, transistor load
102
a
(
FIG. 11
) and the resistance load
102
b
(FIG.
12
).
The charging circuits
106
and
107
operates until the drain electrode of the memory cell
101
b
and the drain electrode of the reference cell
103
b
obtai
Morrison & Foerster / LLP
Nguyen Viet Q.
Sharp Kabushiki Kaisha
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