Reference voltage distribution for multiload i/o systems

Details Reference voltage distribution for multiload i/o systems Reference voltage distribution for multiload i/o systems

1999-12-23

2002-09-17

Dharia, Rupal (Department: 2181)

Electrical computers and digital processing systems: support

Computer power control

C710S100000, C307S147000, C375S257000, C379S090010, C327S537000, C327S538000, C327S546000

Reexamination Certificate

active

06453422

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of receivers. More particularly, the present invention pertains to reference voltage distribution for multiload input/output (i/o) systems.
BACKGROUND OF THE INVENTION
Determination of the state or logic level of a signal (high or low) in digital signaling requires the signal to be compared to a reference state. For example, the signal can be a voltage level, and it can be compared to a reference voltage to determine if the signal is high or low. Providing a reference voltage line which has a reference voltage that tracks noise in a manner similar to the data lines is helpful for achieving high data rates on today's high performance buses. Tracking allows common mode noise rejection at the receiver thereby improving the noise margin. If the reference voltage and the data voltages do not track the noise in a similar manner the amount of time needed for the data signal to clearly cross the reference voltage changes. The amount of time needed for the data signal to clearly cross the reference voltage can vary from one bit to another. However, the worst case time needed for the data signal to clearly cross the reference voltage is used to ensure reliable operation. When the worst case time needed for the data signal to cross the reference voltage increases, the frequency of the data signal has to decrease, making the bus operate at a relatively low data rate. Consequently, it is beneficial for the noise in the reference voltage and data lines to track each other. Tracking noise in both the reference voltage and data lines is commonly referred to as pseudo differential voltage reference (Vref) distribution.
Pseudo differential voltage reference distribution has been implemented for point-to-point complementary metal-oxide semiconductor (CMOS) systems. In point-to-point complementary metal-oxide semiconductor (CMOS) systems a first chip and a second chip both generate the reference voltage(s) and distribute the reference voltage(s) among each other.
FIG. 1
illustrates a CMOS point-to-point network which has pseudo differential Vref distribution implemented in simultaneous bi-directional signaling technology (SBD). CMOS network
100
includes chip
110
and chip
120
. Chip
110
and chip
120
are coupled by data line
115
and reference lines
130
and
140
. Chip
110
generates a high reference voltage (Vhigh) and a low reference voltage (Vlow) which are driven unto reference lines
130
and
140
, respectively. Chip
120
also generates a Vhigh and Vlow which are driven unto reference lines
130
and
140
. Since both chips
110
and
120
continuously and simultaneously generate and distribute the reference voltages the reference voltages are generally well defined at all times.
Chip
110
includes driver
112
, input line
111
, multiplexer
113
, receiver
114
and high voltage reference driver (high vref driver)
142
, and low voltage reference driver (low vref driver)
144
. Chip
120
includes driver
122
, input line
121
, multiplexer
123
, receiver
124
and high voltage reference driver (high vref driver)
146
, and low voltage reference driver (low vref driver)
146
. Driver
112
drives a data signal received on input line
111
onto line
115
. While driver
112
is driving the data signal onto line
115
, reference voltage generators
142
and
144
are applying Vhigh and Vlow onto lines
130
and
140
and reference voltage generators
146
and
148
are also applying Vhigh and Vlow onto lines
130
and
140
. In addition to driving the data signal onto line
115
, driver
112
also couples noise to line
115
. By generating Vhigh and Vlow at both chip
110
and
120
and applying Vhigh and Vlow to lines
130
and
140
, noise in each chip is also coupled to the reference voltage lines
130
and
140
. Since the output impedance of drivers
142
and
146
matches the impedance of drivers
112
and
122
and the lengths of lines
130
and
140
match the length of line
115
noise couples to lines
130
,
140
, and
115
substantially equally helping noise tracking and rejection at receivers
114
and
124
.
Receiver
124
receives the signal on line
115
and the output of multiplexer
123
. Multiplexer
123
either outputs Vhigh or Vlow depending on whether the outbound signal driven is high or low. Receiver compares the signal received on line
115
with the output multiplexer
123
and outputs a signal indicative of the logic level or state of the signal on line
115
. Since noise in line
115
substantially tracks the noise in lines
130
and
140
, the common mode noise can be rejected at the receiver, improving performance. Receiver
114
operates in a manner similar to receiver
124
and need not be described in greater detail here. While only one data line is shown in network
100
, generally multiple data bits share a common Vref pair.
There are other bus technologies besides CMOS SBD technology, each of which has its advantages and which would benefit from pseudo differential voltage reference distribution. Examples of alternative bus technologies include: unidirectional, multi-load CMOS, or multi-load open drain (Gunning transistor logic (GTL)) signaling systems. Since tracking noise in both the reference voltage and data lines and minimizing drift in the reference voltage line(s) may have a beneficial effect on performance and noise margin, it is desirable to give the benefits of pseudo differential voltage reference distribution to unidirectional, multi-load CMOS, or Gunning transistor logic (GTL) signaling systems.
SUMMARY OF THE INVENTION
According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line is described. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.


REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5247209 (1993-09-01), Cheng
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5371424 (1994-12-01), Quigley et al.
patent: 5483110 (1996-01-01), Koide et al.

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