Reference circuit in ferroelectric memory and method for...

Details Reference circuit in ferroelectric memory and method for... Reference circuit in ferroelectric memory and method for...

2002-06-14

2003-07-29

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S210130

Reexamination Certificate

active

06600675

ABSTRACT:

This application claims the benefit of Korean Application No. P2001-38130, filed in Korea on Jun. 29, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a reference circuit in a ferroelectric memory and a method for driving the same, which can stabilize the reference level and enable a reference capacitor to be commonly used by adjacent cell array blocks in order to reduce a layout area.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory device, (i.e., ferroelectric random access memory (FRAM)) has a data processing speed that is substantially the same as a dynamic random access memory (DRAM) and also retains data even in power-off. For this reason, the nonvolatile ferroelectric memory has been highly regarded as a next generation memory device.
As a memory device having a structure similar to that of a DRAM, FRAM uses a high residual polarization, which is a characteristic of ferroelectric, by using ferroelectric as a component of a capacitor. Due to such characteristic of a residual polarization, data remains unerased even if the electric field is removed.
FIG. 1
illustrates a hysteresis loop of a typical ferroelectric. As shown in
FIG. 1
, even if the electric field that induced a polarization is removed, the data is maintained at a certain amount (the “d” and “a” states) due to the presence of the residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is constructed by regarding the “d” and “a” states as “1” and “0”, respectively.
A related art ferroelectric memory device will now be explained with reference to the accompanying drawings.
FIG. 2
is a schematic view of a cell array block of a typical ferroelectric memory, and
FIG. 3
is a circuit diagram of a main cell in FIG.
2
. The cell array block includes a plurality of sub cell arrays. Adjacent top and bottom sub cell arrays sub_T and sub_B are formed, and a sensing amplifier S/A block is formed between the sub cell arrays sub_T and sub_B. That is, one sensing amplifier circuit is correspondingly formed per each bit line, and a column selector CS is formed at the end of the bit line.
Each of the sub cell arrays includes bit line Top_B/L (or Bot_B/L), a plurality of main cells MC connected to the bit line Top_B/L (or Bot_B/L), a reference cell RC connected to the bit lines Top_B/L (or Bot_B/L), and a column selector CS. The column selector CS selectively activates a corresponding column bit line using Y (column) address. If the column selector CS is in the high level, the corresponding column bit line is connected to a data bus to enable data transmission.
The structure of a main cell of the cell array with the aforementioned structure will now be described. As shown in
FIG. 3
, a main cell MC is constructed such that a bit line B/T is formed in one direction, and a word line W/L is formed to cross the bit line. A plate line P/L is spaced apart from the word line W/L in the same direction as the word line W/L. A transistor T with a gate connected to the word line W/L and a source connected to the bit line B/L is formed. A ferroelectric capacitor FC is formed in such a manner that its first terminal is connected to a drain of the transistor T and its second terminal is connected to the plate line P/L.
The structure and operation of a related art reference cell of a ferroelectric memory with the aforementioned structure will now be described.
FIG. 4
is a schematic view of a reference cell of the related art ferroelectric memory. In each reference cell, a bit line B/L is formed in one direction, a reference word line REF_W/L is formed to cross the bit line, a switch block
51
is controlled by a signal on the reference word line to selectively transmit a reference voltage stored in the ferroelectric capacitor bit line. Ferroelectric capacitors are connected to the input terminal of the switching block
51
in parallel. The level initializing block
52
selectively initializes a level of the input terminal of the switching block
51
connected to the ferroelectric capacitors.
The switching block
51
includes an NMOS transistor (also referred to as “first transistor”) T
1
with a gate connected to the reference word line REF_W/L, a drain connected to the bit line B/L, and a source connected to a storage node SN.
The level initializing block
52
is controlled by a reference cell equalizer control signal REF_EQ, which is a control signal for initializing the storage node SN of the reference cell. The level initializing block
52
includes an NMOS transistor (also referred to as “second transistor”) T
2
connected between the source of the first transistor T
1
and a ground terminal Vss.
The number of ferroelectric capacitors FC
1
, FC
2
, FC
3
, FC
4
, . . . , FCn is determined depending on the capacitor size of the reference cell. The storage node SN is connected with first terminals of the ferroelectric capacitors FC
1
, FC
2
, FC
3
, FC
4
, . . . , FCn in parallel. In other words, FC
1
is a basic connection terminal, and FC
2
, FC
3
, FC
4
, . . . , FCn may be provided additionally depending on the need.
The reference cell equalizer control signal REF_EQ initializes the storage node to a ground voltage level. Namely, when the reference cell equalizer control signal REF_EQ is in the high level, the second transistor T
2
is turned on so that the storage node is maintained at a ground voltage level.
The operation of the aforementioned reference cell will now be described. Qs and Qns of a hysteresis loop of a ferroelectric shown in
FIG. 5
denote the switching charge of the ferroelectric capacitor and the non-switching charge of the ferroelectric capacitor, respectively. The reference cell is based on Qns. In other words, the reference word line REF_W/L within the operation cycle is raised to the high level together with the reference plate line REF_P/L. Accordingly, charges equivalent to the size of Qns×(ferroelectric capacitor) are supplied to the bit line B/L. In this case, the reference word line REF_W/L is changed to the low level before the sensing amplifier is operated, so that the reference cell is not affected by a voltage of the bit line. Meanwhile, the reference plate line REF_P/L is maintained at the high level, and is changed to the low level when the reference word line is sufficiently stabilized.
As described above, since non-switching charges Qns are used, a separate restoring operation is not required during a precharge period. Accordingly, the high level in the reference word line REF_W/L is not required any longer than this.
Since the reference level is affected by an initial level of the storage node SN, the second transistor T
2
of
FIG. 4
is used to stabilize the storage node SN, and the reference equalizer control signal REF_EQ is used to initialize the storage node to the ground voltage level. Therefore, since the initial level of the storage is maintained at the ground voltage level, the reference level can be stabilized.
The method of operation will now be described with reference to a hysteresis loop and a timing chart of the reference cell.
FIG. 5
is a hysteresis loop of the reference cell of the related art ferroelectric memory, and
FIG. 6
is a timing chart illustrating the operation of a reference cell according to the related art. Referring to
FIG. 6
, an operation cycle begins as a chip enable signal CEBpad is changed to the low level, so that active periods A, B, and C are formed. A precharge period D begins as the chip enable signal CEBpad is changed to the level. One cycle is completed by passing through the precharge period.
When the active period of the chip begins, an address is decoded during the periods A and B. Then, various control signals are activated, and the reference word line REF_W/L and the reference plate line REF_P/L are changed from the low level to the high level. As the reference word line REF_W/L and the reference plate line REF_P/L are changed from

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