Reference cells with integration capacitor

Details Reference cells with integration capacitor Reference cells with integration capacitor

2002-04-01

2004-02-03

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S145000, C365S149000, C365S203000

Reexamination Certificate

active

06687177

ABSTRACT:

This application claims priority from Canadian Patent application 2,342,508 filed Mar. 30, 2001.
FIELD OF THE INVENTION
The present invention relates to DRAM memories. More particularly the invention relates to bitline reference capacitors used in DRAM memories.
BACKGROUND OF THE INVENTION
Folded bitline DRAM architectures require a reference voltage on the unaccessed bitline of a complementary folded bitline pair in order to sense the voltage potential on the accessed bitline of a complementary folded bitline pair. Prior to a read operation from the memory cells, both bitlines of the complementary bitline pair are precharged to a mid-point voltage level. This mid-point voltage level is approximately a mid-point voltage between the logic “1” voltage potential level and the logic “0” voltage potential level, and can be supplied by voltage generators or through charge sharing by equalizing a pair of bitlines carrying opposite rail-to-rail voltage levels. During a read operation, a wordline is driven to couple a DRAM storage capacitor to one of the bitlines. If the storage capacitor stored a logic “0” charge, then the voltage level of the bitline it is coupled to will drop below the mid-point voltage level. On the other hand, if the storage capacitor stored a logic “1” charge, then the voltage level of the bitline will rise above the mid-point voltage level. The unaccessed bitline of the complementary bitline pair then serves as a reference voltage for the bitline sense amplifier. Unfortunately, the storage capacitor can only change the voltage level of the precharged bitline by a few hundred multi-volts, thus the sensing margin of the bitline sense amplifiers is small and susceptible to mis-reads.
FIG. 1
is a diagram showing the relative bitline voltage levels during a read access operation for prior art DRAM devices. It is assumed that the DRAM memory cells comprise a p-channel access transistor and a planar storage capacitor, and the unaccessed bitline BL is used as the reference bitline in this example. The midpoint voltage level of BL* is reduced through capacitive charge sharing by a memory cell that stores a logical “0” when a wordline WL is driven to the low voltage level. Shortly thereafter, sense amplifier enable signal SN falls to the low logic level to activate the bitline sense amplifiers. The bitline sense amplifiers will detect that the voltage level of BL* is below the mid-point reference voltage of BL and subsequently drive BL* to ground and BL to VDD. The accessed memory cell coupled to BL* is then restored. Mis-reads from the bitlines sense amplifier will not occur if the necessary voltage difference &Dgr;v is maintained between the voltage level of the accessed bitline and the reference voltage of the unaccessed bitline.
However, DRAM memory cells exhibits asymmetrical leakage characteristics. More specifically p-channel memory cells storing a logical “0” tend to leak towards a logical “1” value over time, while p-channel memory cells storing a logical “1” do not leak much charge over time. The dashed BL* line in
FIG. 1
illustrated the effect of coupling a cell that stored a logic “0” and has suffered leakage to BL*. Because the memory cell has leaked towards the logical “1” value BL* is weakly pulled down to a voltage level above the desired level represented by the solid black line. Hence the voltage difference &Dgr;v is reduced and data is unpredictably read because the bitline sense amplifier will not be able to differentiate between the voltage levels of BL and BL*. Furthermore, the memory cell can leak to a point where the level of BL* is increased above the level of BL to cause a misread. A known solution for overcoming this problem is to use reference memory cells connected to each bitline. The reference memory cells, also known as dummy cells, are usually identical to normal memory cells in the memory array. The reference cells are commonly used in full rail bitline precharge schemes. Reference cells or dummy cells can be used to adjust the reference level if either “0” or “1” voltage levels cannot be fully restored. The use of reference cells increases the sense margin to compensate for leakage of the memory cells. Reference cells also provide improved noise immunity and faster sensing, for example.
FIG. 2
is a general diagram of reference cells and an equalization transistor. Each reference cell has a p-channel access transistor with a source terminal connected to a bitline (not shown) and a drain terminal coupled to a storage capacitor. One reference cell has a gate connected to a DWL_ODD reference wordline signal and a drain terminal coupled to storage capacitor C
1
. The other reference cell has a gate connected to a DWL_EVEN reference wordline signal and a drain terminal coupled to storage capacitor C
2
. The equalization transistor is a p-channel transistor connected between the two storage capacitors and having a gate connected to an equalization signal EQ for shorting the two storage capacitors together. Although a common cell plate is shown as a dashed box that covers the areas of C
1
and C
2
, those of skill in the art will understand that the cell plate extends to cover all the storage capacitor areas of the memory array.
In operation, both storage capacitors of the reference cells are initially discharged upon power up of the memory. During the first write operation, both the storage capacitors will be precharged to logic high and logic low levels, or logical “1” and “0” levels and then equalized to a mid-point voltage level. A dummy memory cell is then coupled to the unaccessed bitline of a complementary bitline pair during a sense operation from an accessed bitline. When a weak or leaked logic “0” is read from the accessed bitline, the voltage difference between the two bitlines is sufficient for the bitline sense amplifiers to latch the data. After the data is fully latched by the bitline sense amplifiers, the reference cell of the accessed bitline is turned on. Now both storage capacitors C
1
and C
2
store complementary voltage levels. Therefore, when the wordlines are turned off and the equalisation transistor is turned on, charge is shared equally between C
1
and C
2
such that both their voltage levels should be at the mid-point voltage level. Although a p-channel equalisation transistor is shown, one skilled in the art should understand that an p-channel transistor would work equally well.
Although the use of reference cells in the above mentioned application can improve sense margins for memory cells leaking stored logical “0” levels, misreads can still occur if the reference cells themselves are not adequately charged to the mid-point voltage level. This problem occurs in high speed memory operations where the cycle time is too short to allow the reference cell to be fully restored prior to a subsequent operation, or if the access transistor wordline cannot be sufficiently boosted to pass the full voltage level. This problem also occurs if the restoration cycle is sufficiently different from the cycle used to restore sensed cells, and is more prevalent following write operations, as the write operation is typically shorter in duration than a read operation, leaving less time available for restoring the charges of the reference cells. The latter problem typically occurs in planar memory cells that utilize low voltage transistors. For example, one reference cell may not be able to store full logic “1” level while the other reference cell stores a full logic “0” level. When equalized, both reference cells will have stored a reference voltage less than the mid-point voltage level. This will degrade the capability of bitline sense amplifiers to accurately read out data from an accessed bitline, and in particular, from a leaking memory cell.
Therefore, there is a need for a reference cell equalisation circuit that compensates for reference cells that are unable to equalize to a mid-point voltage level for reliable bitline sensing operations. There is also a need for a reference cell arrangement that allows for fast equalisati

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