Reference cells for TCCT based memory cells

Details Reference cells for TCCT based memory cells Reference cells for TCCT based memory cells

2002-06-10

2004-08-24

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C323S273000

Reexamination Certificate

active

06781888

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor capacitively coupled negative differential resistance (“NDR”) devices for data storage, and more particularly to reference cells to be used therewith.
2. Description of the Prior Art
U.S. Pat. No. 6,229,161 issued to Nemati et al., incorporated herein by reference in its entirety, discloses capacitively coupled NDR devices for use as SRAM memory cells. The cells disclosed by Nemati et al. are hereinafter referred to as thinly capacitively coupled thyristor (“TCCT”) based memory cells.
FIG. 1
shows a pair of representative TCCT based memory cells
10
as disclosed by Nemati et al., and
FIG. 2
shows a cross-section through one TCCT based memory cell
10
along the line
2
—
2
.
FIG. 3
shows a schematic circuit diagram corresponding to the embodiment illustrated in
FIGS. 1 and 2
. The TCCT based memory cell
10
includes an NDR device
12
and a pass transistor
14
. A charge-plate or gate-like device
16
is disposed adjacent to, and in the case of the illustrated embodiment, surrounding, the NDR device
12
. A P+ region
18
of the NDR device
12
is connected to a metallization layer
20
so that a first voltage V
1
, such as V
ddarray
, can be applied to the NDR device
12
through the P+ region
18
. An N+ region of the NDR device
12
forms a storage node
22
that is connected to a source of the pass transistor
14
. Where the pass transistor
14
is a MOSFET, it can be characterized by a channel length, L, and a width, W, where L is the spacing between the source and the drain, and W is the width of the pass transistor
14
in the direction perpendicular to the page of the drawing in FIG.
2
. Assuming a constant applied voltage, a current passed by pass transistor
14
will scale proportionally to a ratio of W/L.
Successive TCCT based memory cells
10
are joined by three lines, a bit line
26
, a first word line (WL
1
)
28
, and a second word line (WL
2
)
30
. The bit line
26
connects a drain
32
of pass transistor
14
to successive TCCT based memory cells
10
. In a similar fashion, pass transistor
14
includes a gate
34
that forms a portion of the first word line
28
. Likewise, the gate-like device
16
forms a portion of the second word line
30
.
Memory arrays of the prior art typically include a large number of memory cells that are each configurable to be in either of two states, a logical “1” state or a logical “0” state. The memory cells are typically arranged in rows and columns and are connected to a grid of word lines and bit lines. In this way any specific memory cell can be written to by applying a signal to the appropriate word lines. Similarly, the state of a memory cell is typically manifested as a signal on one of the bit lines. In order to correctly interpret the state of the memory cell from the signal on the bit line, memory arrays of the prior art typically rely on some form of a reference signal against which the signal on the bit line is compared.
One type of memory array of the prior art uses SRAM cells for the memory cells. A conventional SRAM cell stores a voltage and includes two access ports, data and data-bar, where data-bar is a complementary signal to data and serves as a reference. A sensing circuit for the conventional SRAM cell compares the voltages of data and data-bar to determine whether the SRAM cell is storing a “1” or a “0.”
Another type of memory array of the prior art uses DRAM cells for the memory cells. A conventional DRAM cell is a capacitor and stores a charge to represent a logical state. When a DRAM cell is read it produces a voltage on a bit line. A typical reference cell for a DRAM memory array is a modified DRAM cell designed to store about half as much charge as the conventional DRAM cell. Accordingly, in a DRAM memory array the voltage produced by the DRAM cell is compared to the voltage produced by the reference cell to determine whether the DRAM cell is storing a “1” or a “0.”
In comparison to the conventional SRAM cell, a TCCT based memory cell
10
has only a single port, namely bit line
26
. In further comparison to both the SRAM and DRAM cells, the TCCT based memory cell
10
does not produce a voltage but instead produces a current. More specifically, TCCT based memory cell
10
has an “on” state wherein it generates a current that is received by bit line
26
. TCCT based memory cell
10
also has an “off” state wherein it produces essentially no current. Accordingly, voltage-based reference cells of the prior art are inadequate for determining the state of a TCCT based memory cell
10
and a new type of reference is needed.
A reference cell to be used in a memory array of TCCT based memory cells
10
should produce a reference current with an amount that is somewhere within the range defined by the currents generated by TCCT based memory cell
10
in the “on” and “off” states, and preferably about half the magnitude of the current generated by TCCT based memory cell
10
in the “on” state. It is well known, however, that the amount of current produced by TCCT based memory cell
10
varies as a function of temperature, variations in manufacturing, operating conditions (i.e., voltages), among other things. Therefore, what is desired is a reference cell capable of generating a reference current that will remain at a suitable magnitude such as about half the intensity of the current generated by a TCCT based memory cell
10
in the “on” state despite variations in manufacturing and operating conditions.
SUMMARY
A reference cell for a TCCT based memory cell includes an NDR device, a switch, and a current reduction element arranged together with a bit line and two word lines. The NDR device includes a doped semiconductor layer between first and second ends, the first end configured to have a first voltage applied thereto. The NDR device also includes a gate-like device disposed adjacent to the doped semiconductor layer. The switch is preferably a pass transistor that includes a source coupled to the second end of the NDR device, a drain, and a gate coupled to the first word line. The second word line is coupled to the gate-like device. The current its reduction clement is coupled between the bit line and the drain of the pass transistor. In some embodiments the current reduction element is a second pass transistor including a gate having a second voltage applied thereto. In these embodiments the reference cell produces an amount of current that is sufficient to be used as a reference. By applying an appropriate voltage to the second pass transistor, the second pass transistor can be made to have an appropriate resistance such that the desired current reduction is obtained.
These embodiments are advantageous in that a reference cell can be made to be in every respect the same as a TCCT based memory cell with the additional feature of a current reduction element. This way a reference current produced by the reference cell will be less than the amount of current produced by the TCCT based memory cell in the “on” state. In other embodiments the same advantages are achieved with an NDR device as described coupled to a single pass transistor. In these embodiments a voltage is applied to a gate of the single pass transistor such that it produces a resistance equal to the sum of the resistances of the first and second pass transistors in the previous embodiments.
Other embodiments of the invention are directed to a circuit for generating a reference voltage to control a current output of a reference cell. These embodiments allow the current output from a reference cell of the invention to be continuously maintained at any desired value, though preferably at about half of the amount of current produced by a TCCT based memory cell. The circuit to generate a reference voltage includes a TCCT based memory cell to produce a first current, a pair of reference cells as described above, each producing a current, and a feedback circuit. In these embodiments the reference cell p

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