Reference cell configuration for a 1T/1C ferroelectric memory

Details Reference cell configuration for a 1T/1C ferroelectric memory Reference cell configuration for a 1T/1C ferroelectric memory

2000-09-15

2001-06-26

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S203000, C365S210130, C365S202000

Reexamination Certificate

active

06252793

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to ferroelectric memories. More particularly, the present invention relates to those memories employing an array of one-transistor, one-capacitor (“
1
T/
1
C”) ferroelectric memory cells.
2. Description of the Prior Art
The first designs with ferroelectric capacitors utilized memory cells containing two transistors and two ferroelectric capacitors, (“
2
T/
2
C”). Ferroelectric
2
T/
2
C memory products are shown and described in the 1996 Ramtron International Corporation FRAM® Memory Products databook, which is hereby incorporated by reference. A
2
T/
2
C memory is also described in U.S. Pat. No. 4,873,664 entitled “Self Restoring Ferroelectric Memory”, which is also hereby incorporated by reference. The
2
T/
2
C memory cells were arranged in a physical layout such that the transistors and the ferroelectric capacitors were adjacent in the cell.
FIG. 1
is a schematic diagram of a
2
T/
2
C memory cell and also represents the relative proximity of the physical layout of the elements. Ferroelectric memory cell
10
includes a first transistor M
1
coupled to a first ferroelectric capacitor CC, and a second transistor M
2
coupled to a second ferroelectric capacitor CCb. Ferroelectric capacitors CC and CCb store complementary polarization states, which define a single data state of memory cell
10
. The plate line PL, which is coupled to one side of the ferroelectric capacitors CC and CCb runs parallel to the word line WL, which is coupled to the gates of the two transistors M
1
and M
2
. In the arrangement of
FIG. 1
, the signal propagation delay along the plate line PL across one cell is insignificant compared to the delay in transferring data from the cell to the complementary bit lines BL and BLb, which are coupled to the source/drains of transistors M
1
and M
2
. In the schematic of
FIG. 1
, the connection between the common electrodes for capacitors CC and CCb is a plate line wire PL. This plate line wire is a highly conductive material, generally a metal conductor. Also, the physical layout of memory cell
10
places these elements in close proximity to each other.
A timing diagram for the operation of a
2
T/
2
C memory cell such as cell
10
is shown in FIG.
3
. The control signals necessary to develop charge on the complementary bit lines BL and BLb are the word line signal WL and the plate line signal PL. The word line waveform
12
is a pulse that transitions from ground to the VCC supply voltage. The plate line waveform
14
,
16
can either be a shorter or longer pulse, depending upon the desired sensing method. Initially, the word line and plate line waveforms are at ground potential. At time t
0
, the word line waveform is taken high to the VCC power supply voltage level, which turns on transistors M
1
and M
2
and electrically couples the ferroelectric capacitors CC and CCb to the bit lines BL and BLb, respectively. Once the high voltage level has been established on the word line, the plate line is pulsed to “pole” the ferroelectric capacitors at time t
1
. Plate line waveform
14
is used for the “up-down” sensing method. With reference to the hysteresis loop
38
of
FIG. 10
, the “up-down” sensing method senses the charge developed moving from point
1
to point
2
to point
3
of the “switched” ferroelectric capacitor, minus the charge developed moving from point
3
to point
2
back to point
3
in the “unswitched” ferroelectric capacitor. Note that waveform
14
is brought low to ground potential at time t
2
. At time t
3
the sense amplifiers (not shown in
FIG. 1
) are enabled and the differential charge on the bit lines BL and BLb can be sensed and converted into a valid logic state. Plate line waveform
16
is used for the “up-only” sensing method. With reference again to the hysteresis loop
38
of
FIG. 10
, the “up-only” sensing method senses the charge developed moving only from point
1
to point
2
in the “switched” ferroelectric capacitor minus the charge moving from point
3
to point
2
of the “unswitched” ferroelectric capacitor. Note that plate line waveform
16
remains high at times t
2
and t
3
. At time t
3
the sense amplifiers are enabled and the differential charge on the bit lines can be sensed and again converted into a valid logic state. Although the charge in each case is slightly different, the charge from the switched ferroelectric capacitor in cell
10
is always larger than the charge from the unswitched capacitor, so that the correct data state can be sensed.
In the full array of memory cells
10
, bit lines are paired as true/complement and connected as illustrated in FIG.
4
. Each block
10
is a
2
T/
2
C memory cell as shown in previous FIG.
1
. In the arrangement of
FIG. 4
, there is a multiplicity of paired plate lines PL
0
through PLN and word lines WL
0
through WLN extending in the word or row direction. There is a corresponding multiplicity of pairs of true/complement bit lines BL
0
/BLb
0
through BLN/BLbN in the column or bit direction.
Using the physical layout corresponding to the array of
FIG. 4
, the data pattern along the bit lines is always in pairs of true complement data. Therefore, no matter what logical data pattern is written into the array, the bit line data pattern as described by “1's” and “0's” representing the actual high and low voltages on the bit lines is described completely by the pattern “
10
” plus its complement “
01
”. This is not to be confused with the logical data states of “
1
” and “0” that refers to a pair of bit lines, such as BL
0
and BLb
0
. The “1” or “0” referred to below represents the high “1” and low “0” voltage on each pair of bit (BL
0
-BLN) and bit bar (BLb
0
-BLbN) bit lines shown in
FIGS. 1 and 4
. Any other larger array of cells repeats this basic pattern. Assuming eight columns for the array shown in
FIG. 4
, corresponding to 16 bit/bit bar pairs, the pattern combinations could be, for example, 1010101010101010, 0101010101010101, 1001100110011001 or 0110011001100110. Because of the nature of the cell layout with true complement data per cell there is never an accumulated pattern of all “1's” or all “1's” or of isolated bits such as all “1's” with a single zero or its complement as illustrated by the following 16 bit sequences: 1111111101111111 or 0000000010000000. Again, each individual “1” or “0” represents the voltage on an individual bit line wire.
Patterns such as that described above having single “0's” or “1's” in a field of opposite polarity can be created, however, in a
1
T/
1
C memory design, depending on the chip architecture. These patterns create cumulative noise on the bit lines within an array. When the sense amplifiers are latched, noise generated through capacitive coupling between bit lines reduces the operating margin of the single bit line of opposite polarity. A schematic of a
1
T/
1
C DRAM cell
20
coupled to a single bit line BL for a single storage location is shown in FIG.
5
. One side of conventional oxide capacitor CC is connected to the access transistor M
1
and the other side is connected to a node
22
that is common to all memory cells in a DRAM array. The common node
22
is usually at a potential of one half of the VCC power supply voltage, for example 2.5 volts for a five volt power supply voltage.
The ferroelectric version of the
1
T/
1
C DRAM memory cell
20
of
FIG. 5
is shown in FIG.
2
. Ferroelectric memory cell
18
also includes a single access transistor M
1
, which is coupled to a ferroelectric capacitor CC. A single word line WL is coupled to the gate of access transistor M
1
and a single bit line BL is coupled to the source/drain of access transistor M
1
. Instead of a common node
22
as in the DRAM cell
20
, ferroelectric memory cell
18
includes an individual active plate line PL per word line as shown in FIG.
2
.
The noise problem described above with reference to a
1
T/
1
C array occurs when an “open bit line” architecture is used. In this configuration, all the true

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