Reference cell configuration for a 1T/1C ferroelectric memory

Static information storage and retrieval – Systems using particular element – Ferroelectric

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365149, 365205, 365207, 365208, G11C 700

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active

059869194

ABSTRACT:
A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

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