Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-01-31
2001-05-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185010, C365S196000, C365S185330
Reexamination Certificate
active
06226213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state memory device in the reading operation, and more particularly to a novel reference cell array which generates a criterion reference current for doing a comparison between the normal bit line and the reference bit line by a sense amplifier. The state stored in the normal cell is hence judged.
2. Description of the Prior Art
In recent years, the development of the portable telecommunications and laptop computers has become a major driving force in the design and technology of semiconductor IC's. This growing market requires low power, high-density and electrically re-writable nonvolatile memories. Electrically erasable programmable read only memories (EEPROM) which are electrically erased on a byte-by-byte basis is one choice, however, the cell size of this type of memory is too large for application, and thus the flash memory is another choice because of its small size and high reliability. A typical prior art circuitry for reading the state stored in a flash memory is best illustrated by reference to FIG.
1
.
FIG. 1
shows several functional blocks for illustrating the read operation to the memory cell. There are upper reference cell array
10
, lower reference cell array
20
, upper normal memory cell array
30
, and lower normal memory cell array
40
, as well as a sense amplifier
50
. The voltage of the selected flash cell
30
a
in the bottom normal cell array
30
and the reference voltage of the bit line
10
a
in the upper reference array
10
will compare the sense amplifier
50
in the read operation. On the other hand, the voltage of the selected flash cell
40
a
in the upper normal cell array
40
will compare the voltage of the reference bit line
20
a
in the bottom reference array
20
. The arrangement is to set the discharge current of the selected cell and of the reference bit line being at the same time delay.
In the reading operation, the sense amplifier
50
is pre-charged to a “high state” by turning on a precharge transistor (not shown). The selected word line of the memory cell and reference word line are also through a corresponding X decoder (not shown) selection so as to set them at an active state, and so does the reference bit line and the selected memory cell bit line. Thereafter, the precharge transistor is turned off to remove the precharge state of the sense amplifier
50
. The cell current of the selected flash cell
40
a
is through a bit line in the bottom normal cell array
40
to discharge and the reference current is through a reference bit line in the upper reference array
10
to discharge. The sense amplifier
50
then compares the voltage difference between them to determine whether the data stored in the cell is logic high or logic low. As usual, the threshold current of the reference current is set to be of ½ to ⅓ of a normal cell when it is at precharge state. The “⅓” is usually a preferred value.
In the conventional method, the reference cell array consists of cells and NMOS transistors. Each reference bit line connects a cell and a NMOS transistor. For setting the reference discharge current to be of ⅓ of the normal cell, the NMOS transistor sizes are adjusted. However, it would be dangerous because of different performance behaviors of the NMOS transistor and the cell. The variation of the cell size or process will affect the reference discharge current if the size of the transistor is not adjusted again.
Thus an object of the present invention is to design a novel reference cell array so as to solve the aforementioned problems.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a reference bit line voltage for a normal cell reading. The reference bit line voltage is about ⅓ of the normal cell.
A novel reference cell array for normal cell reference is disclosed. The reference cell array comprises three word lines in the upper portion and three in the lower portion. Two portions are separated by a common source line. The common source line connects common sources of the middle two rows cells to a ground potential. Each bit line has a bit line contact and an isolation region being respectively distributed at different portions and is like a black-white grid on a checkerboard to ensure the selected bit line connects only three cells. In addition, all floating gates are coupled to a potential reference to define their states and the middle four word lines are also coupled to a power source and the left exterior two connected to a X_decoder to a select one.
Since a reference bit line connects only three serial cells, a value of about ⅓ of normal cell current is naturally obtained. Still because the reference cell is the same type as the normal cell it will easily to trace the cell size variation and hence be easily handled.
REFERENCES:
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5657332 (1997-08-01), Auclair et al.
patent: 5737260 (1998-04-01), Takata et al.
patent: 5754475 (1998-05-01), Bill et al.
patent: 6091618 (2000-07-01), Fazio et al.
Le Thong
Nelms David
Taiwan Semiconductor Manufacturing Co. Ltd.
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