Reed Solomon decoding of signals having variable input data...

Details Reed Solomon decoding of signals having variable input data... Reed Solomon decoding of signals having variable input data...

2011-07-26

2011-07-26

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S772000, C714S776000

Reexamination Certificate

active

07987412

ABSTRACT:
A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for Reed Solomon decoders, and can lead to reduced buffering, resulting in significant hardware savings.

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patent: 6480976 (2002-11-01), Pan et al.
patent: 6550035 (2003-04-01), Okita

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