Reed-solomon decoder using a configurable arithmetic processor

Details Reed-solomon decoder using a configurable arithmetic processor Reed-solomon decoder using a configurable arithmetic processor

2011-01-11

2011-01-11

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07870468

ABSTRACT:
A Reed Solomon decoder utilizes re-configurable and re-usable components in a granular configuration which provides an upper array and a lower array of repeated Reconfigurable Elementary Units (REU) which in conjunction with a FIFO can be loaded with syndromes and correction terms to decode Reed Solomon codewords. The upper array of REUs and lower array of REUs handle the Reed Solomon decoding steps in a pipelined manner using systolic REU structures. The repeated REU includes the two registers, two Galois Field adders, a Galois Field multiplier, and multiplexers to interconnect the elements. The REU is then able to perform each of the steps required for Reed-Solomon decoder through reconfiguration for each step using the multiplexers to reconfigure the functions. In this manner, a reconfigurable computational element may be used for each step of the Reed-Solomon decoding process.

REFERENCES:
patent: 5610929 (1997-03-01), Yamamoto
patent: 6615387 (2003-09-01), Williamson et al.

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