Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-12-21
2002-11-26
Baker, Stephen M. (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06487692
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of decoders utilized in digital communication systems for providing Forward Error Correction (FEC) and more particularly to a Reed-Solomon decoder capable of correcting two symbol errors in a codeword of a Reed-Solomon RS(128,122,7) code over a Galois field GF(128).
BACKGROUND OF THE INVENTION
Forward Error Correction (FEC) is a communications technique commonly used to correct errors occurring in data during transmission. Such errors may occur during transmission or storage for a number of reasons, for example, noise or interference in the transmission, or the like. Using FEC, data is processed through an algorithm that adds extra bits for error correction prior to transmission. If, when received, the transmitted data includes errors, the correction bits are used to repair the data.
Reed-Solomon codes, which are a subset of Bose-Chadhuri-Hocquenghm (BCH) linear block codes, are commonly used to provide forward error correction (FEC) in a variety of storage and communications systems, including tape, compact disc (CD), digital video disc (DVD), barcodes, cellular telephones, microwave links, satellite communications, digital television, high speed modems, and the like. In a typical Reed-Solomon system, an encoder takes a block of digital data and adds extra “redundant” bits. The Reed-Solomon decoder processes each block and attempts to correct errors occurring during transmission to recover the original data. The number and type of errors that can be corrected depends on the characteristics of the Reed-Solomon code.
To meet present cable modem standards, existing Reed-Solomon decoders utilized in cable modems, for instance, Berlekamp-Massey and Euclidean algorithm based decoders, attempt to correct three errors in a received codeword of an extended RS (128,122,7) code. However, correction of two errors, if possible, would be sufficient to meet present cable modem standards. Consequently, existing RS(128,122,7) decoders are unnecessarily complex. Consequently, it is desirable to provide a Reed-Solomon decoder capable of correcting two symbol errors in a codeword of an extended Reed-Solomon RS(128,122,7) code over a Galois field GF(128).
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a decoder for a digital communication system providing Forward Error Correction (FEC), wherein the decoder employs a novel method of correcting up to two symbol errors in a codeword of a linear block code. In one embodiment, the present invention is directed to a Reed-Solomon decoder capable of correcting up to two symbol errors in a codeword of a Reed-Solomon code, in particular, a Reed-Solomon RS(128,122,7) code over a Galois field GF(128). In an exemplary embodiment, the Reed-Solomon decoder is suitable for use in cable modems with little or no loss in error performance over Reed-Solomon decoders correcting three errors in a codeword.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5379305 (1995-01-01), Weng
patent: 5615221 (1997-03-01), Karp et al.
patent: 5841378 (1998-11-01), Klayman et al.
patent: 6081920 (2000-06-01), Morelos-Zaragoza
Fenn et al., “Decoding Double-Error-Correcting Reed-Solomon Codes”, IEE Proc.-Commun, vol. 142, No. 6, Dec. 1995, pp. 345-348,*
Wolf, “A DSP Reed-Solomon Coder”, IEEE 1999, Custom Integrated Circuits Conference, pp. 541-544.
Baker Stephen M.
LSI Logic Corporation
Suiter & Associates PC
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