Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1996-11-27
1999-03-30
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711140, 711169, 711114, 707204, 39518204, G06F 1216
Patent
active
058902198
ABSTRACT:
An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. Each control processor is responsible for 2 pipelines and respective Direct Multiple Access (DMA) and Direct Single Access (DSA) pipelines, for Global Memory access. Each processor has its own Memory Data Register (MDR) to support DMA/DSA activity. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides. Pipelines are extended to add greater depth by incorporating a prefetch mechanism that permits write data to be put out to transceivers awaiting bus access, while two full buffers of assembled memory data are stored in Dual Port Ram and memory data words are assembled in pipeline gate arrays for passing to DPR. Data prefetch mechanisms are included whereby data is made available to the bus going from Global Memory on read operations, prior to the bus being available for an actual data transfer. Two full buffers of read data are transferred from Global Memory and stored in DPR while data words are disassembled in the pipeline gate array, independent of host activity. Timing of system operations is implemented such that there is overlap of backplane requests to transfer data to/from memory, memory selection and data transfer functionality.
REFERENCES:
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5490261 (1996-02-01), Bean et al.
patent: 5504861 (1996-04-01), Crockett et al.
patent: 5544347 (1996-08-01), Yanai et al.
patent: 5557763 (1996-09-01), Senter et al.
patent: 5590309 (1996-12-01), Chencinski et al.
patent: 5617347 (1997-04-01), Lauritzen
patent: 5617559 (1997-04-01), Le et al.
patent: 5619664 (1997-04-01), Glew
Scaringella Stephen Lawrence
Sne Gal
Tung Victor Wai Ner
EMC Corporation
Kim Hong
Michaelis Brian L.
Swann Tod R.
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