Redundant type memory circuit with an improved clock generator

Details Redundant type memory circuit with an improved clock generator Redundant type memory circuit with an improved clock generator

1984-05-04

1988-02-02

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

365194, 365195, G11C 800

Patent

active

047232277

ABSTRACT:
A redundant type memory circuit having a normal memory cell array, a first decoder circuit for operatively accessing normal array, a redundant memory cell array, a second decoder circuit for accessing the redundant array, and a programmable timing control circuit for enabling the first decoder circuit at a first delay period when no faulty cell exists in the normal array and at a second longer delay period when a faulty cell exists in the normal array.

REFERENCES:
patent: 4576455 (1985-10-01), Iwahashi et al.

Affiliated with

Also associated with

Rating

Redundant type memory circuit with an improved clock generator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundant type memory circuit with an improved clock generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundant type memory circuit with an improved clock generator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1638859