Redundant-storage memory

Details Redundant-storage memory Redundant-storage memory

1987-11-30

1989-08-29

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 700, G11C 800

Patent

active

048624179

ABSTRACT:
A memory incorporates redundancy in the form of one or more redundant columns. An applied binary address is first distributed between predecoders which form a 1-out-of-2.sup.n code from n bits received. For each non-redundant column there is available a part of a main decoder, each part receiving a different combination of the bits supplied by the predecoders, thus selecting the column. For each redundant column there is provided a redundancy decoder. The latter decoder receives all bits supplied by the predecoders, each time via a series connection of a activatable gating element and a fuse element. Per predecoder the outputs of the series connections are combined in a wired logic function. Each wired logic function forms an input signal of the actual redundancy decoder. When a redundant column is to be addressed, all fuse elements but one of a group are opened and the gating elements are activated. A memory column to be replaced is then uncoupled by way of another fuse element.

REFERENCES:
patent: 4598388 (1986-07-01), Anderson
patent: 4720817 (1988-01-01), Childers
patent: 4737935 (1988-04-01), Wawersig et al.
patent: 4748597 (1988-05-01), Saito et al.

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