Redundant row topology circuit, and memory device and test syste

Details Redundant row topology circuit, and memory device and test syste Redundant row topology circuit, and memory device and test syste

1999-02-22

2000-08-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

060976446

ABSTRACT:
An integrated circuit includes a memory-cell array having a plurality of memory cells arranged in rows and columns. The memory-cell array includes at least one redundant memory cell, each of the memory cells having an associated data topology. A data path circuit transfers data between an external terminal and the memory-cell array. The data path circuit sets the data topology between data on the external terminal and data at the array responsive to a data topology signal. An address decoder receives an address applied on an address bus and further receives a matching signal. The address decoder accesses memory cells in the memory-cell array responsive to the address and matching signals. A data topology circuit is coupled to the address decoder and the data path circuit, and includes a programmable topology element. In response to the address having a predetermined value, the data topology circuit applies the matching signal to the address decoder to access a predetermined redundant memory cell in the array. The data topology circuit further operates responsive to the matching signal going active and the state of the programmable topology element to apply the data topology signal to the data path circuit to adjust the data topology of the accessed redundant memory cell.

REFERENCES:
patent: 5218572 (1993-06-01), Lee et al.

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