Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-05-16
2001-11-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06324105
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to electronic circuits, and more particularly to a circuit and method for replacing defective memory cells in a memory device with redundant memory cells having the same data topology as the replaced memory cells.
BACKGROUND OF THE INVENTION
A typical semiconductor memory device includes a memory-cell array containing a plurality memory cells arranged in rows and columns. The memory cells in the array are typically tested and, if necessary, repaired before the memory devices are shipped to customers. During testing of the memory device, any of the memory cells that is found to be defective is replaced with a redundant memory cell. The entire row or column containing the defective memory cell is typically replaced with a redundant row or column, respectively. In the following description, it will be assumed that a row containing a defective memory cell is replaced with a redundant row. To replace a row containing a defective memory cell, a row address decoder is programmed to map a redundant row to the address of the row containing the defective memory cell, and to disable data access to the row containing the defective memory cell. Therefore, when an external circuit reads data from or writes data to this detective row address, the row address decoder does not activate the defective row, but instead activates the redundant row so that data may be transferred to or from a corresponding addressed memory cell within the redundant row. This rerouting of the defective row address to the redundant row is often called the repair solution for the memory-cell array.
Replacing defective rows with redundant rows as described above presents a difficulty for thereafter testing the memory cells due to the potential differences between the “data topologies” of the defective and redundant rows. The data topology of a particular row of memory cells defines the relationship between external logic levels applied on a data bus of the memory device and the resulting logic level signals applied on digit lines coupled to the memory cells, as will now be described in more detail with reference to FIG.
1
.
FIG. 1
is a schematic of a portion of a memory-cell array
10
in a conventional dynamic random access memory (“DRAM”). The memory-cell array
10
includes a primary array
11
having N rows of memory cells
12
, the memory cells in each row being coupled to a corresponding word line WL
1
-WLN. The memory-cell array
10
further includes a redundant array
13
having M rows of memory cells
14
, the memory cells in each row being coupled to a corresponding redundant word line RWL
1
-RWLM. Typically, the rows of memory cells
14
in the redundant array
13
are merely additional rows of memory cells in the primary array
11
that are utilized to replace defective rows in the primary array
11
, as will be explained in more detail below. Each of the memory cells
12
and
14
includes a corresponding access transistor
16
and storage capacitor
18
coupled in a conventional manner as shown.
The primary array
11
and redundant array
13
share common complementary digit lines D and {overscore (D)}, each memory cell
12
,
14
in a particular column being coupled to one of the complementary digit lines as shown. The array
10
is a conventional folded-digit-line architecture so the memory cells
12
,
14
in each odd row are coupled to digit line D, and the memory cells
12
,
14
in each even row are coupled to the complementary digit line {overscore (D)}. For example, each memory cell
12
coupled to the word line WL
1
is coupled to the corresponding digit line D while each memory cell
12
coupled to the word line WL
2
is coupled to the corresponding complementary digit line {overscore (D)}. A sense amplifier
15
senses data stored in an addressed memory cell
12
,
14
coupled to one of the complementary digit lines D and {overscore (D)} as understood by those skilled in the art.
During testing of the array
10
, a memory tester (not shown) must apply appropriate logic level signals on external data bus lines (not shown) of the memory device so that the proper logic level signals are applied on the digit lines D and {overscore (D)} and thereafter transferred to the addressed memory cell
12
,
14
. In other words, the memory tester must determine the data topology for each row so that the logic level signals applied on the external data bus result in the desired logic level signals being applied on the digit lines D and {overscore (D)}. For example, suppose the memory tester must transfer a logic 1 to each memory cell
12
and
14
, and that a logic 1 corresponds to a positive voltage of V
CC
/2 being stored across the storage capacitor
18
. Further assume the tester must drive a logic 1 onto an external data pin to force the sense amplifier
15
to drive a logic 1 onto the digit line D and a logic 0 onto the digit line {overscore (D)}, and a logic 0 onto the external data pin to force the sense amplifier to drive a logic 0 onto line D and a logic 1 onto line {overscore (D)}. In this situation, the memory tester must adjust for the different row topologies of even and odd rows. When the tester is addressing odd rows, the tester must apply a logic 1 on the external data pin to cause a logic 1 to be applied on the digit lines D and thereafter transferred to the memory cells
12
,
14
in the addressed odd row. In contrast, if the memory tester is addressing an even row, the tester must apply a logic 0 on the external data pin in order to cause a logic 1 to be applied on the digit lines {overscore (D)} and then transferred into the memory cells
12
,
14
in the addressed even row.
When replacing a defective row with a redundant row, a change in data topology can result if the topologies between the rows are different. As a result, the memory tester must also determine such changes in data topology resulting from the replacement of defective rows with redundant rows of the opposite data topology. A memory tester capable of storing and adjusting for such data topology changes would be a relatively expensive piece of test equipment. Moreover, during testing after defective rows have been replaced, a plurality of memory devices are typically tested in parallel. Therefore, even if an expensive memory tester capable of storing the changes in data topologies is used, it would have to store the different topologies for each of the memory devices being tested in parallel. Unfortunately, even the most sophisticated testers often lack the ability to store such multiple data topologies for the respective memory devices under test Furthermore, even if a memory tester could store multiple topologies, the time required to calculate and store the topology for each memory device could be long enough to considerably slow down the “throughput” of the tester. Similarly, if circuitry were included in the memory device to calculate the data topologies such circuitry would be relatively complex and thus occupy valuable area on the device.
There is a need for replacing defective rows of memory cells in memory devices with redundant rows while maintaining the same row topology between the defective and redundant rows.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, an integrated circuit includes a memory-cell array having a plurality of memory cells arranged in rows and columns. The memory-cell array includes at least one redundant memory cell, each of the memory cells having an associated data topology. A data path circuit transfers data between an external terminal and the memory-cell array. The data path circuit sets the data topology between data on the external terminal and data at the array responsive to a data topology signal. An address decoder receives an address applied on an address bus and further receives a matching signal. The address decoder accesses memory cells in the memory-cell array responsive to the address and matching signals. A data topology circuit is coupled to the address decoder and the data path circuit, and includ
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nelms David
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