Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2000-06-22
2002-11-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S200000, C365S210130, C365S230060
Reexamination Certificate
active
06477102
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a redundant programmable circuit, and more particularly to a redundant programmable circuit which has a small chip area and can be operable while consuming little electric power, and also to a semiconductor memory device including the same.
2. Description of the Related Art
In order to improve the yield, some semiconductor memory devices include a spare memory cell (redundant memory cell) storing data for any defective memory cell (storage device). Such semiconductor memory devices include a redundant circuit for accessing the spare memory cell. The redundant circuit converts an address signal for requesting access to the defective memory cell into an address signal for accessing the spare memory cell.
Such a redundant circuit detects an address signal for requesting access to the defective memory cell, thus always needs to monitor any address signal sent from an external device to the semiconductor memory device. Hence, the redundant circuit, in general, includes a redundant programmable circuit having a fuse element.
FIG. 1
is a diagram showing an example of a conventional redundant programmable circuit. The redundant programmable circuit
160
shown in
FIG. 1
stores data corresponding to one bit of an address signal, in accordance with an operational state of an inverter
166
and an N-channel type MOS transistor
168
. The data which the redundant programmable circuit
160
stores is determined in accordance with whether a fuse element
162
is disconnected therefrom or not.
In the case where the fuse element
162
is disconnected therefrom, a voltage at the input terminal of the inverter
166
is a ground voltage, thus the inverter
166
outputs a high level voltage. As a result of this, the voltage output by an inverter
172
is at a low level, and the N-channel type MOS transistor
168
is in an ON state. In this case, a selection signal S is retained at a low level.
In the case where the fuse element
162
is not disconnected therefrom, an input voltage of the inverter
166
is determined based on a ratio of resistance of the fuse element
162
to resistance of a resistor
164
. The resistance of the resistor
164
is, in general, sufficiently large, the input voltage of the inverter
166
is substantially at the same voltage level as that of a source voltage (VDD). Thus, the inverter
166
outputs a low level voltage. As a result of this, the voltage which the inverter
172
outputs is at a high level, and the N-channel type MOS transistor
168
is in an OFF state. In this case, the selection signal S is retained at a high level.
The resistors
164
and
170
are manufactured using high resistance polysilicon. Conventionally, a number of SRAM (Static Random Access Memory) cells included high resistance polysilicon. Therefore, the redundant programmable circuit
160
could be manufactured in the processes which are the same as those for manufacturing SRAM cells.
Of late, at the request for miniaturization and low-power-consumption of transistors, a source voltage driving the SRAM has gradually been decreased. If the source voltage decreases, the amount of current flowing through a high resistor included in each SRAM cell becomes decreases as well. The decrease in the current amount causes a low operational speed of the SRAM or deterioration in data storage characteristics of the memory cell.
In consideration of the above facts, in each SRAM cell, a CMOS circuit has begun to be utilized in place of high resistance polysilicon. If the CMOS circuit is employed in an SRAM cell, the manufacturing processes for forming, using high resistance polysilicon, the resistors
164
and
170
included in the redundant programmable circuit
160
can not be adapted for manufacturing the SRAM cells. If the resistance of the resistors
164
and
170
decreases, the electric power to be consumed dramatically increases. From the above reasons, an SRAM employing a CMOS circuit may possibly include the redundant programmable circuit
180
illustrated in FIG.
2
.
For example, Unexamined Japanese Patent Application KOKAI Publication No. H10-55693 discloses a technique for improving operational characteristics of the redundant programmable circuit
180
. The entire contents of this publication are incorporated herein by reference.
In the above case, two fuse elements are necessary for one bit address signal. As compared with any other devices, each fuse element needs a large area in a chip, resulting in increasing the chip area of the SRAM.
Unexamined Japanese Patent Application KOKAI Publication No. H7-98983 discloses a redundant controller which employs a circuit, wherein the resistor
164
is replaced with an N-channel type MOS transistor. The entire contents of this publication are incorporated herein by reference.
In the circuit disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H7-98983, a source voltage is supplied to the gate electrode of an N-channel type MOS transistor, thus the amount of current flowing through transistors can not appropriately be controlled. Thus, the technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H7-98983 may cause an increase in the electric power to be consumed.
SUMMARY OF THE INVENTION
It is accordingly an object of this invention to provided a circuit, which is small in size and requires a small amount of electric power, for detecting an address signal for requesting access to any defective memory cells.
In order to achieve the above-described object, according to the first aspect of the present invention, there is provided a redundant programmable circuit comprising:
a control signal generation circuit which has a fuse and generates a control signal in accordance with whether the fuse is disconnected; and
a transfer gate which receives an address signal and outputs an inverted or non-inverted address signal in accordance with the control signal.
According to this invention, the control signal generation circuit has only one fuse, achieving the small chip area.
In this structure, a current controller which is connected to the control signal generation circuit controls an operational current to a given value. This can restrain the electric power to be consumed.
In order to achieve the above object, according to the second aspect of the present invention, there is provided a redundant programmable circuit, comprising:
a plurality of signal output circuits which are connected to a pair of connection lines, and each of which receives a binary signal corresponding to a plurality of bits sent from an external device, and also each of which outputs an inverted or non-inverted binary signal;
a coincidence detection circuit which generates a detection signal representing that the binary signals respectively output by the plurality of signal output circuits are at a predetermined signal level; and
a current controller which controls an amount of current flowing to and through the pair of connection lines to a given value.
According to this invention, the current controller controls an amount of current flowing through the pair of connection lines at a given value. The pair of connection lines are parallelly connected to the plurality of signal output circuits. In this structure, an operational current of the plurality of signal output circuits can be controled, realizing operations of the signal output circuits with little electric power.
In the redundant programmable circuit, each of the plurality of signal output circuits may include:
a transistor and a fuse element which are connected in series between one of the pair of connection lines and a power source;
a voltage retaining circuit which receives a voltage at a connection point of the fuse element and the transistor, and outputs a signal at a given voltage level; and
a transmission circuit which outputs the received binary signal in an inverted or non-inverted form, in accordance with a voltage level of the signal which the volta
NEC Corporation
Yoha Connie C.
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