Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-03-13
2003-06-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230020
Reexamination Certificate
active
06574155
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a redundant multiplexer for a semiconductor memory configuration for replacing two faulty bit lines by two redundant bit lines, in which information which is stored in fuses and relates to which bit lines are to be replaced is used to produce control and switching signals in a decoder. And in which two redundant areas with the redundant bit lines on both sides of a central bus can be selected by the control and switching signal.
When testing semiconductor memory configurations, the person carrying out the test generally has to decide to burn or to select fuses associated with a faulty bit line that is present, in order in this way to replace the faulty bit line by a redundant bit line.
However, a serious problem occurs if it is necessary to take account of the position of the first faulty bit line, which has already been replaced by a first redundant bit line, when assigning a redundant bit line to a second faulty bit line. This is the situation with the latest generation of redundant multiplexers for eDRAMs.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a redundant multiplexer for a semiconductor memory configuration that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the position of a first faulty bit line which has been replaced by a redundant bit line is taken into account when assigning a second redundant bit line which is intended to replace a second faulty bit line.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory configuration having two redundant bit line areas with redundant bit lines, fuses storing information relating to which of the bit lines are to be replaced, a decoder connected to the fuses and receiving the information and the decoder generating control and switching signals from the information relating to the bit lines to be replaced, and a central bus disposed between the two redundant bit line areas. A redundant multiplexer for the semiconductor memory configuration is provided for replacing two faulty bit lines by two of the redundant bit lines. The redundant multiplexer contains a plurality of series connected switches, and two of the control and switching signals for in each case two of the series connected switches are compared to determine whether the series connected switches are set correctly depending on a number of the faulty bit lines.
According to the invention and in the case of a redundant multiplexer of the type mentioned initially, the object is achieved in that the two control and switching signals for in each case two series-connected switches in the multiplexer are compared in order to determine whether the switches are set correctly depending on the number of faulty bit lines.
Thus, in the redundant multiplexer according to the invention, comparators are located between each two series-connected switches. The comparators compare the decoded address (“1” or “0”) sent to each switch with the control and switching signal and, if appropriate, interchange these addresses, if this is necessary, in order that the faulty address which is relatively close in the central redundant areas controls those switches which are relatively close to the memory cell array. Satisfaction of this condition is the only way to prevent data to be read from faulty bit lines. Such faulty reading can thus be precluded by interchanging the addresses by use of the comparators between the switches. When a fault in a first bit line occurs in a semiconductor memory configuration having the redundant multiplexer according to the invention, then the present invention allows a first set of fuses to be burnt in order to correct this fault by the faulty bit line being replaced by a redundant bit line. If a second fault is then found in another bit line, so that there is a second faulty bit line, a second set of fuses can be burnt, and this is done independently of the fault that was determined initially. Therefore, the fault which was determined initially does not need to be stored in a tester once the first set of fuses has been burnt. This makes it possible to save memory space in the tester without any problems.
In conventional configurations, faults need to be stored in the tester since it is necessary to determine the sequence of replacement operations before fuses can be burnt. In the present invention, this sequence is determined directly, so that a fuse can be burnt immediately when a fault occurs.
In accordance with an added feature of the invention, a comparator is disposed between each two of the series connected switches.
In accordance with another feature of the invention, the series connected switches are set such that a faulty control and switching signal with an address which is stored relatively close in the redundant line areas controls those of the series connected switches which are disposed relatively close in a memory cell array of the semiconductor memory configuration.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a redundant multiplexer for a semiconductor memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5493531 (1996-02-01), Pascucci et al.
patent: 6118727 (2000-09-01), Allan et al.
patent: 6363020 (2002-03-01), Shubat et al.
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