Redundant memory circuit for analog semiconductor memory

Details Redundant memory circuit for analog semiconductor memory Redundant memory circuit for analog semiconductor memory

2002-01-30

2003-11-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S185090, C365S185110

Reexamination Certificate

active

06643196

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog semiconductor memory such as an analog audio flash memory and, more particularly, to a redundant analog semiconductor memory circuit in which bad sectors are replaced with redundant sectors.
2. Description of the Related Art
As shown in
FIGS. 1A and 1B
, an analog audio flash memory comprises an input pad
1
, an input amplifier
2
, an input low-pass filter (LPF)
3
, a write gate voltage generating circuit
4
(known also as a programming voltage generating circuit, referred to below as a VPP circuit), a memory circuit
13
including an address decoder
5
and a memory cell section
6
, a shift voltage generating circuit (VSFT circuit)
7
, a sense amplifier circuit (SA-AMP circuit)
8
, a read gate voltage generating circuit
9
(known also as a verify voltage generating circuit, referred to below as a VVFY circuit), an analog output circuit
10
(known also as a shifted playback output circuit, referred to below as an SHPLYO circuit), an output low-pass filter (LPF)
11
, and an output pad
12
. The elements in
FIG. 1A
pertain to the recording process (the writing or programming of the audio signal into the memory); the elements in
FIG. 1B
pertain to the playback or reproduction process (the reading of the recorded audio signal from the memory).
In the recording process, an analog input voltage AIN
1
representing an analog audio signal is received at the input pad
1
and supplied to the non-inverting input terminal of the input amplifier
2
. An internally generated analog signal reference potential SG is supplied to the inverting input terminal of the input amplifier
2
. The input amplifier
2
subtracts the analog signal reference potential SG from the input audio signal voltage AIN
1
to generate an input audio signal voltage AIN, which is supplied to the input low-pass filter
3
. This low-pass filter
3
rejects noise components and harmonics present in the input audio signal voltage AIN, and supplies the resulting filtered signal to the VPP circuit
4
.
The VSFT circuit
7
generates an analog input shift voltage VSFT
1
, which is supplied to the VPP circuit
4
. The purpose of the analog input shift voltage VSFT
1
is to shift the input audio signal voltage AIN upward to a voltage suitable for programming memory cells. The shifting is carried out by the VPP circuit
4
, which thereby generates a programming voltage VPP, referred to below as a write gate voltage, responsive to the input audio signal voltage AIN. The write gate voltage VPP is supplied to the address decoder
5
and applied to memory cells in the memory cell section
6
. More specifically, the address decoder
5
writes the audio signal in the memory cell section
6
by sequentially selecting the memory cells in the memory cell section
6
and applying the write gate voltage VPP to the gate electrodes of transistors in the selected memory cells.
Referring to
FIG. 1B
, when the signal is reproduced, the VVFY circuit
9
generates a variable verify voltage VVFY, referred to below as a read gate voltage. The address decoder
5
sequentially selects the memory cells in the memory cell section
6
, applies the read gate voltage VVFY to the gates of transistors in the selected memory cells, and outputs the signal read from each memory cell (the memory cell signal ICELL) to the sense amplifier (SA-AMP) circuit
8
. The sense amplifier circuit
8
converts the memory cell signal ICELL to a sense amplifier output signal SAOUT which goes either high or low. The VVFY circuit
9
varies the read gate voltage VVFY while monitoring the sense amplifier output signal SAOUT, and finds the VVFY value at which SAOUT switches between high and low; this value is the threshold voltage of the memory cell being read. The VSFT circuit
7
generates an analog output shift voltage VSFT
2
, which is similar to the analog input shift voltage VSFT
1
mentioned above but is supplied to the analog output (SHPLYO) circuit
10
. The purpose of the analog output shift voltage VSFT
2
is to shift the read gate voltage VVFY down to a value equivalent to the original input audio signal voltage AIN. When the read gate voltage VVFY has settled at the memory cell threshold value, the SHPLYO circuit
10
samples the VVFY value, shifts the sampled value down according to the analog output shift voltage VSFT
2
, thereby generates an output analog signal SHPLYO equivalent to the original input audio signal voltage AIN, and outputs SHPLYO to the output low-pass filter
11
. This low-pass filter
11
rejects noise components and harmonic components present in the output analog signal SHPLYO, and outputs the filtered signal to the output pad
12
.
An analog audio flash memory is a type of multi-level memory, in that each memory cell stores a value that can range over many different levels. In the present case, the analog voltage of the audio signal is sampled periodically, and each sample is written as an analog value into one memory cell, as the threshold voltage of a transistor in the memory cell. When the signal is reproduced, the stored values (threshold voltages) are read out as analog values. Accordingly, more information can be stored per memory cell than in a digital flash memory, in which each memory cell stores only a single bit of information (0 or 1). Moreover, the need for analog-to-digital and digital-to-analog conversion is eliminated.
Conventional Redundant Memory Circuit
To lengthen the recording and playback times of audio flash memory chips, memory capacities are being increased, necessitating fabrication processes with increasingly smaller feature sizes, and reduced yields due to defective memory cells have become a problem. To keep yields from declining, it has become common to incorporate a redundancy replacement function into the memory circuit
13
, by providing redundant memory cells.
FIG. 46
shows the overall layout of a conventional redundant memory circuit comprising a predecoder PDEC and four memory units UMEU
0
, UMEU
1
, UMEU
2
, UMEU
3
. The notation UMEU will be used below to denote any one of these four memory units. The memory units include redundant sectors, indicated by hatching.
FIG. 47
shows the layout of a memory unit UMEU in more detail. The memory unit UMEU includes four cell arrays UCLA, (individually denoted UCLA-LU, UCLA-RU, UCLA-LD, UCLA-RD), four word line decoders WLDEC (WLDEC-LU, WLDEC-RU, WLDEC-LD, WLDEC-RD), four bit-line decoders UBLDEC (UBLDEC-LU, UBLDEC-RU, UBLDEC-LD, UBLDEC-RD), and four source line decoders USLDEC (USLDEC-LU, USLDEC-RU, USLDEC-LD, USLDEC-RD).
Each cell array UCLA has its own word line decoder WLDEC, bit line decoder UBLDEC, and source line decoder USLDEC. The memory cell section
6
in
FIGS. 1A and 1B
comprises sixteen cell arrays. The address decoder
5
in
FIGS. 1A and 1B
comprises the predecoder, the sixteen word line decoders, the sixteen bit line decoders, and the sixteen source line decoders.
Cell Arrays of the Conventional Redundant Memory Circuit
A cell array UCLA comprises sixty-four sectors SC (SC
0
, SC
1
, . . . , SC
63
) and one redundant sector RSC. The cell array UCLA has two hundred fifty-six word lines WL (WL
0
, WL
1
, . . . , WL
255
), five hundred twelve bit lines BL (BL
0
, BL
1
, . . . , BL
511
), sixty-four source lines SL (SL
0
, SL
1
, . . . , SL
63
), eight redundant bit lines RBL (RBL
0
, RBL
1
, . . . , RBL
7
), and one redundant source line RSL. This cell array UCLA, incidentally is derivable by adding a redundant sector RSC, redundant bit lines RBL
0
to RBL
7
, and a redundant source line RSL to a non-redundant cell array, shown in
FIG. 3
, which will be described later.
The word lines WL
0
-WL
255
are controlled by the word line decoder WLDEC, the bit lines BL
0
-BL
511
and RBL
0
-RBL
7
by the bit line decoder UBLDEC, and the source lines SL
0
-SL
63
and RSL by the source line decoder USLDEC.
Each sector SC (and the redundant sector RSC) is a two-kilocell array comprising two thousand forty-eight memory cells. (A kilocell is 2
10

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