Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1983-04-18
1986-03-18
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Bad bit
365 96, 371 10, G11C 1140, G11C 700
Patent
active
045772940
ABSTRACT:
A redundant memory circuit having a memory for storing information in a matrix of interconnected rows and columns, and a row and a column address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder which is programmed with the row address of the defective row to access the redundant row. The row and column address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit can be used to verify that the redundant row can be accessed and that the programmable decoder is properly programmed to decode only one address to one row.
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J. Cocke, "Read and Test to Reduce Redundancy Requirements in Memories", IBM Tech. Disclosure Bulletin, vol. 15, No. 3, Aug. 1972, pp. 885-886.
Brown George W.
Thai Phi
Advanced Micro Devices , Inc.
Gossage Glenn A.
Hecker Stuart N.
King Patrick T.
Rosenberg Gerald B.
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