Redundant memory circuit

Details Redundant memory circuit Redundant memory circuit

1982-11-01

1985-07-30

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 1300

Patent

active

045326118

ABSTRACT:
A circuit is provided in MOS technology which replaces a defective row of memory cells with a redundant row of memory cells in response to the address of the defective row and an implementation signal. The defective row is disabled by a floating gate fusible link which responds to the output of the decoder of the defective row as driven by the address thereof and to the implementation signal. The redundant row is implemented by floating gate fusible links which disable the inputs of the decoder of the redundant row which correspond to complements of the address in response to the address and the implementation signal. The implemented redundant row then receives address signals without any additional propagation delays.

REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4250570 (1981-02-01), Tsang et al.

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