Redundant memory architecture with defragmentation capability

Details Redundant memory architecture with defragmentation capability Redundant memory architecture with defragmentation capability

2006-03-28

2006-03-28

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230080, C365S233100

Reexamination Certificate

active

07020032

ABSTRACT:
A redundant memory architecture having an active memory and an inactive memory. The active memory supports in-service storage operations. The inactive memory is updated with stored contents of the active memory. Stored contents of the inactive memory are defragmented prior to an activity switch that results thenceforth in the inactive memory assuming the in-service storage operations and the active memory being updated with the stored contents of the inactive memory. The redundant memory architecture further has a data structure to maintain correspondence between the stored contents of the active memory and those of the inactive memory.

REFERENCES:
patent: 6453404 (2002-09-01), Bereznyi et al.
patent: 6714467 (2004-03-01), Terzioglu et al.
patent: 6763017 (2004-07-01), Buckingham et al.

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