Redundant link delay maintenance circuit and method

Details Redundant link delay maintenance circuit and method Redundant link delay maintenance circuit and method

1998-05-26

2002-05-14

Chin, Stephen (Department: 2734)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S013000, C375S372000

Reexamination Certificate

active

06389553

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to methods and systems for interconnecting a circuit with a set of two or more redundant circuits.
BACKGROUND OF THE INVENTION
It is common for communications circuits to come in redundant pairs in which one of the pair is active at a given time. Should the active circuit fail, the second circuit takes over the role of the active circuit. If such a redundant pair is communicating with a third circuit, conventional systems include a first link from the first of the redundant pair to the third circuit and a second link from the second of the redundant pair to the third circuit. While improving technology is making the circuits themselves faster, cheaper and more reliable, the electrical interconnect for such links between circuits is on the other hand more mature. The cost of multi-card circuits can be reduced, and the reliability improved, by reducing the amount of interconnect between the circuits. This may be done by time-multiplexing various data streams that flow between the circuits into serial, high-speed data links.
Typically in a scenario in which a redundant pair of circuits is connected to a third circuit over first and second time multiplexed links, the delay over the first link is different from the delay over the second link, and as such when the active circuit of the redundant pair is switched the timing of the data received by the third circuit changes.
This presents a problem in delay sensitive functions, such as some wireless transmission paths, in which the delay in the transmit path must be fixed and deterministic. This also presents a problem if the third circuit requires constant timing.
SUMMARY OF THE INVENTION
It is an object of the invention to obviate or mitigate one or more of the above identified disadvantages.
According to a first broad aspect, the invention provides an apparatus comprising: a data buffer; a link receiver for receiving an input data stream and for recovering link timing information from the input data stream, and for writing the input data stream to the data buffer on the basis of the link timing information; local timing circuitry for generating stable local timing information from the recovered link timing information and for reading data from the data buffer on the basis of the local timing information and for outputting this in an output data stream.
According to a second broad aspect, the invention provides an apparatus comprising: a data buffer; a link receiver for receiving an input data stream and for recovering link timing information from the input data stream, and for writing the input data stream to the data buffer on the basis of the link timing information; local timing circuitry for generating stable local timing information from the recovered link timing information and for reading data from the data buffer on the basis of the local timing information and for outputting this in an output data stream.
According to a third broad aspect, the invention provides a method of maintaining a stable delay variation in a circuit which is connected to receive an input data stream which is subject to delay variation, the method comprising the steps of: receiving data from the input data stream; generating link timing information on the basis of the selected data stream; writing the received data to a data buffer on the basis of the link timing information; generating relatively stable local timing information on the basis of the link timing information; and reading data from the data buffer on the basis of the local timing information and outputting the read data in an output data stream.


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